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| Presentation | 2011-04-12 13:00 An Approach and Evaluation of Fault Tolerant Sequential Circuits for Simultaneous Occurrence of Multiple Transient Faults Satoshi Fukumoto, Kenta Imai, Hideo Kohinata, Masayuki Arai (Tokyo Metropolitan Univ.)  CPSY2011-1 DC2011-1 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper discusses the extension of highly reliable technique for sequential circuits using duplicate register which has been already presented by author's research group. A new approach by triplicate register enables the circuit to recover even in the case that simultaneous occurrence of multiple transient faults continues for 2 clock cycles. The concrete microprocessor for applying this technique is constructed to exhibit actually enhanced dependability. Overhead on circuit area is estimated and the fault tolerance under our assumptions is confirmed. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | transient fault / highly reliable sequential circuit / simultaneous multiple faults / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 2, DC2011-1, pp. 1-4, April 2011. | |
| Paper # | DC2011-1 | |
| Date of Issue | 2011-04-05 (CPSY, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2011-1 DC2011-1 |
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| Conference Information | |
| Committee | DC CPSY |
| Conference Date | 2011-04-12 - 2011-04-12 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2011-04-DC-CPSY |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Approach and Evaluation of Fault Tolerant Sequential Circuits for Simultaneous Occurrence of Multiple Transient Faults |
| Sub Title (in English) | |
| Keyword(1) | transient fault |
| Keyword(2) | highly reliable sequential circuit |
| Keyword(3) | simultaneous multiple faults |
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| 1st Author's Name | Satoshi Fukumoto |
| 1st Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
| 2nd Author's Name | Kenta Imai |
| 2nd Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
| 3rd Author's Name | Hideo Kohinata |
| 3rd Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
| 4th Author's Name | Masayuki Arai |
| 4th Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
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| Speaker | Author-2 |
| Date Time | 2011-04-12 13:00:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | CPSY2011-1, DC2011-1 |
| Volume (vol) | vol.111 |
| Number (no) | no.1(CPSY), no.2(DC) |
| Page | pp.1-4 |
| #Pages | 4 |
| Date of Issue | 2011-04-05 (CPSY, DC) |
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