Paper Abstract and Keywords |
Presentation |
2011-04-12 14:30
[Invited Talk]
Tamper LSI Design Methodology Resistant to Malicious Attack Takeshi Fujino, Mitsuru Shiozaki (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Univ.) CPSY2011-4 DC2011-4 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Tamper LSI Design Methodology have to be applied in order to implement secure cryptographic circuit which is resistant to side-channel attack such as DPA (Differential Power Analysis). The principle of DPA and some typical countermeasures against DPA are introduced and discussed the problem on the LSI implementation. The domino-RSL technique, which randomizes the output transition rate by the random number, is easy to implement in the conventional LSI design flow. The DES cryptographic circuit was designed by this technique, and a good DPA resistance is demonstrated on the test chip. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Tamper Resistant LSI / Side-Channel Attack / DPA / CPA / WDDL / RSL / Domino-RSL / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 2, DC2011-4, pp. 17-22, April 2011. |
Paper # |
DC2011-4 |
Date of Issue |
2011-04-05 (CPSY, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2011-4 DC2011-4 |
Conference Information |
Committee |
DC CPSY |
Conference Date |
2011-04-12 - 2011-04-12 |
Place (in Japanese) |
(See Japanese page) |
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(See Japanese page) |
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Paper Information |
Registration To |
DC |
Conference Code |
2011-04-DC-CPSY |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Tamper LSI Design Methodology Resistant to Malicious Attack |
Sub Title (in English) |
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Keyword(1) |
Tamper Resistant LSI |
Keyword(2) |
Side-Channel Attack |
Keyword(3) |
DPA |
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CPA |
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WDDL |
Keyword(6) |
RSL |
Keyword(7) |
Domino-RSL |
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1st Author's Name |
Takeshi Fujino |
1st Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
2nd Author's Name |
Mitsuru Shiozaki |
2nd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
3rd Author's Name |
Masaya Yoshikawa |
3rd Author's Affiliation |
Meijyo University (Meijyo Univ.) |
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Speaker |
Author-1 |
Date Time |
2011-04-12 14:30:00 |
Presentation Time |
60 minutes |
Registration for |
DC |
Paper # |
CPSY2011-4, DC2011-4 |
Volume (vol) |
vol.111 |
Number (no) |
no.1(CPSY), no.2(DC) |
Page |
pp.17-22 |
#Pages |
6 |
Date of Issue |
2011-04-05 (CPSY, DC) |
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