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| Presentation | 2011-03-04 15:55 Evaluation of Wiring Resource and Wiring Delay used in Via Programmable Logic Device VPEX Tatsuya Kitamori, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.)  VLD2010-147 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We have developed a via programmable logic device using exclusive-or array (VPEX). In a VPEX, the logic is changed using the 1st via layer, and each wiring between logic elements is performed using the 3rd via layer. In this paper, we evaluate the interconnect delay of VPEX and the wiring resource of one. The VPEX delay increases in number of via and redundancy in wires by via programmable wire. We simulate and measure the delay model using in ring oscillator circuit. The design flows of the conventional ASIC and VPEX are compared to find the difference in the wiring delay wire resource. The results show that the wiring delay in the critical path of the VPEX increases about 1.5 times compared with the ASIC. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Via Programmable Device / Wire delay / Redundant wire / Routing architecture / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 432, VLD2010-147, pp. 183-188, March 2011. | |
| Paper # | VLD2010-147 | |
| Date of Issue | 2011-02-23 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2010-147 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2011-03-02 - 2011-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawaken-Danjo-Kyodo-Sankaku Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2011-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Wiring Resource and Wiring Delay used in Via Programmable Logic Device VPEX |
| Sub Title (in English) | |
| Keyword(1) | Via Programmable Device |
| Keyword(2) | Wire delay |
| Keyword(3) | Redundant wire |
| Keyword(4) | Routing architecture |
| Keyword(5) | |
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| Keyword(8) | |
| 1st Author's Name | Tatsuya Kitamori |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 2nd Author's Name | Ryohei Hori |
| 2nd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 3rd Author's Name | Taisuke Ueoka |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 4th Author's Name | Masaya Yoshikawa |
| 4th Author's Affiliation | Meijo University (Meijo Univ.) |
| 5th Author's Name | Takeshi Fujino |
| 5th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-03-04 15:55:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2010-147 |
| Volume (vol) | vol.110 |
| Number (no) | no.432 |
| Page | pp.183-188 |
| #Pages | 6 |
| Date of Issue | 2011-02-23 (VLD) |
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