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| Presentation | 2011-03-04 14:25 Write Optimization for High-speed Non-volatile Memory Using Next State Function Naoya Okada (Waseda Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.)  VLD2010-144 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Non-volatile memory, such as MRAM and PCM, attracts attention for reducing power consumption. However, it consumes large write energy and has the limitation on the number of write operation. Therefore, it is desirable to reduce redundant writes for Non-volatile memory. In this manuscript, a detection method of redundant writes is proposed based on the next state function. If the next state does not depend on some current bit, the bit is redundant and unnecessary to write. Experiment results on ISCAS'89 benchmark circuits show that 0.45%～50.78% writes are redundant. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | state transition analysis / write reduction / high-speed non-volatile memory / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 432, VLD2010-144, pp. 165-170, March 2011. | |
| Paper # | VLD2010-144 | |
| Date of Issue | 2011-02-23 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2010-144 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2011-03-02 - 2011-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawaken-Danjo-Kyodo-Sankaku Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2011-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Write Optimization for High-speed Non-volatile Memory Using Next State Function |
| Sub Title (in English) | |
| Keyword(1) | state transition analysis |
| Keyword(2) | write reduction |
| Keyword(3) | high-speed non-volatile memory |
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| 1st Author's Name | Naoya Okada |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Yuichi Nakamura |
| 2nd Author's Affiliation | NEC Corporation (NEC) |
| 3rd Author's Name | Shinji Kimura |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-03-04 14:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2010-144 |
| Volume (vol) | vol.110 |
| Number (no) | no.432 |
| Page | pp.165-170 |
| #Pages | 6 |
| Date of Issue | 2011-02-23 (VLD) |
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