Paper Abstract and Keywords |
Presentation |
2011-03-04 13:10
An evaluation of error detection/correction circuits by gate level simulation Masafumi Inoue (Tokyo Tech.), Yuuta Ukon, Atsushi Takahashi (Osaka Univ.) VLD2010-141 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In a typical synchronous circuit design, the maximum delay between flip-flops gives a lower bound of the clock period such that no delay error occurs in the circuits. In the error detection/correction mechanism, however, the occurence of delay errors is allowed, and so all design constraints related to the maximum delay are relaxed. This allows a circuit to perform speculative executions. Therefore, the performance of the circuit would be increased when the gain obtained by permitting delay errors overcomes the loss for the error/correction. In this paper, we investigate an implementation of the error detection/correction mechanism and evaluate the validity and perfomance of it by gate-level simulation.
We confirm that 10% speed up of the adder-accumulator designed in our approach compared to the one designed in typical framework is achieved. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
error detection/correction / delay error / design constraint / gate-level simulation / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 432, VLD2010-141, pp. 147-152, March 2011. |
Paper # |
VLD2010-141 |
Date of Issue |
2011-02-23 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2010-141 |
Conference Information |
Committee |
VLD |
Conference Date |
2011-03-02 - 2011-03-04 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawaken-Danjo-Kyodo-Sankaku Center |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for System-on-Silicon |
Paper Information |
Registration To |
VLD |
Conference Code |
2011-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An evaluation of error detection/correction circuits by gate level simulation |
Sub Title (in English) |
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Keyword(1) |
error detection/correction |
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delay error |
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design constraint |
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gate-level simulation |
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1st Author's Name |
Masafumi Inoue |
1st Author's Affiliation |
Tokyo Institute of Technology (Tokyo Tech.) |
2nd Author's Name |
Yuuta Ukon |
2nd Author's Affiliation |
Osaka University (Osaka Univ.) |
3rd Author's Name |
Atsushi Takahashi |
3rd Author's Affiliation |
Osaka University (Osaka Univ.) |
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Speaker |
Author-1 |
Date Time |
2011-03-04 13:10:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2010-141 |
Volume (vol) |
vol.110 |
Number (no) |
no.432 |
Page |
pp.147-152 |
#Pages |
6 |
Date of Issue |
2011-02-23 (VLD) |
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