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| Presentation | 2011-03-03 11:25 A Low Power Hardware Architecture for Parallel Group Signature Computation Sumio Morioka, Jun Furukawa, Kazue Sako (NEC)  VLD2010-128 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We've investigated architecture of H/W accelerators for parallel group signature computation, which will be used in data centers in order to process multiple number of authentication requests simultaneously. If the accelerator is constructed by simply arranging single-signature circuits, the total power consumption can be large because a lot of arithmetic units waste power in the suspended state. In this paper, we incorporated a H/W architecture where arithmetic units are shared between different request-processing and low-power arithmetic units are also used. Our evaluation results show that 30-50 percent reduction of total power consumption is possible, as compared to the simple parallel architecture, without degrading TAT. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | anonymous authentication / group signature / H/W architecture / parallel processing / accelerator / low-power design / ESL / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 432, VLD2010-128, pp. 69-74, March 2011. | |
| Paper # | VLD2010-128 | |
| Date of Issue | 2011-02-23 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2010-128 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2011-03-02 - 2011-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawaken-Danjo-Kyodo-Sankaku Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2011-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Low Power Hardware Architecture for Parallel Group Signature Computation |
| Sub Title (in English) | |
| Keyword(1) | anonymous authentication |
| Keyword(2) | group signature |
| Keyword(3) | H/W architecture |
| Keyword(4) | parallel processing |
| Keyword(5) | accelerator |
| Keyword(6) | low-power design |
| Keyword(7) | ESL |
| Keyword(8) | |
| 1st Author's Name | Sumio Morioka |
| 1st Author's Affiliation | NEC Corporation (NEC) |
| 2nd Author's Name | Jun Furukawa |
| 2nd Author's Affiliation | NEC Corporation (NEC) |
| 3rd Author's Name | Kazue Sako |
| 3rd Author's Affiliation | NEC Corporation (NEC) |
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| Speaker | Author-1 |
| Date Time | 2011-03-03 11:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2010-128 |
| Volume (vol) | vol.110 |
| Number (no) | no.432 |
| Page | pp.69-74 |
| #Pages | 6 |
| Date of Issue | 2011-02-23 (VLD) |
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