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| Presentation | 2011-03-02 13:35 Energy-Aware Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors with Multi-Cycle Instructions Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.)  VLD2010-117 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Reducing energy consumption is a crucial for the embedded system design, and especially, the leakage energy reduction is now big problem for the low power design. In order to reduce the leakage energy at standby time, power gating scheme is well known as a promising technique to realize partial power shutdown. However, the power gating usually causes cycle and energy overheads. In this paper, we propose energy aware instruction scheduling considering multi cycle instructions for fine gained power gated VLIW processors. Proposed scheduling algorithm is formulated by 0-1 ILP (integer linear programming). | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Instruction Scheduling / Low Power Design / VLIW Processors / Power Gating / 0-1Integer Linear Programming / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 432, VLD2010-117, pp. 7-12, March 2011. | |
| Paper # | VLD2010-117 | |
| Date of Issue | 2011-02-23 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2010-117 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2011-03-02 - 2011-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawaken-Danjo-Kyodo-Sankaku Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2011-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Energy-Aware Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors with Multi-Cycle Instructions |
| Sub Title (in English) | |
| Keyword(1) | Instruction Scheduling |
| Keyword(2) | Low Power Design |
| Keyword(3) | VLIW Processors |
| Keyword(4) | Power Gating |
| Keyword(5) | 0-1Integer Linear Programming |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Mitsuya Uchida |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 2nd Author's Name | Ittetsu Taniguchi |
| 2nd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 3rd Author's Name | Hiroyuki Tomiyama |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 4th Author's Name | Masahiro Fukui |
| 4th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-03-02 13:35:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2010-117 |
| Volume (vol) | vol.110 |
| Number (no) | no.432 |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2011-02-23 (VLD) |
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