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| Presentation | 2011-03-02 15:05 An Energy-efficient ASIP Synthesis Method Using Scratchpad Memory and Code Placement Optimization Yoshinori Shimada, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)  VLD2010-120 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, we propose an energy-efficient ASIP synthesis method using scratchpad memory. Due to the fact that a significant amount of power is consumed in the instruction memory, how to develop energy-efficient memory structure becomes important in reducing the overall power consumption of the system. Our method is based on the idea of using scratchpad memory with code placement optimization. The proposed memory architecture can copy data from instruction memory to scratchpad memory under the control of on-chip program counter. With an inputted application CFG, the proposed code placement optimization is used to decide both the code allocations and the required scratchpad memory size for energy minimization. By doing this, the total energy consumption could be reduced as the number of instruction memory accesses is reduced. Experimental results on Mediabench are included to show the effectiveness of the proposed method, in which on average 47.9% energy consumption could be reduced. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | ASIP / energy consumption / scratchpad memory / instruction memory / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 432, VLD2010-120, pp. 25-30, March 2011. | |
| Paper # | VLD2010-120 | |
| Date of Issue | 2011-02-23 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2010-120 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2011-03-02 - 2011-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawaken-Danjo-Kyodo-Sankaku Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2011-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Energy-efficient ASIP Synthesis Method Using Scratchpad Memory and Code Placement Optimization |
| Sub Title (in English) | |
| Keyword(1) | ASIP |
| Keyword(2) | energy consumption |
| Keyword(3) | scratchpad memory |
| Keyword(4) | instruction memory |
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| 1st Author's Name | Yoshinori Shimada |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Youhua Shi |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Nozomu Togawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Masao Yanagisawa |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
| 5th Author's Name | Tatsuo Ohtsuki |
| 5th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-03-02 15:05:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2010-120 |
| Volume (vol) | vol.110 |
| Number (no) | no.432 |
| Page | pp.25-30 |
| #Pages | 6 |
| Date of Issue | 2011-02-23 (VLD) |
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