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| Presentation | 2011-02-18 15:25 Logic stabilization of unstable logic circuit with open fault Taiki Yasutomi, Masaru Sanada (KUT)  R2010-47 EMD2010-148 Link to ES Tech. Rep. Archives: EMD2010-148 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | An experiment for stabilization of output logic brought by floating gate fault with unsuitable electric value has been executed. The method is the way to apply outside laser irradiation to inverter circuit with gate open fault. The experimental result indicated that output value was stabilized to “H” level, and IDD value is simultaneously changed. This valuation value corresponds to operation point in normal IN-OUT characteristics. Another experiment which Laser was irradiated to one side of two inverter circuits with common gate line showed to stabilize to the other side output value. This phenomenon is explained combining with single Transistor experiment. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Floating gate fault / Stabilized logic value / Laser irradiation / Inverter circuit / Middle voltage / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 415, R2010-47, pp. 31-36, Feb. 2011. | |
| Paper # | R2010-47 | |
| Date of Issue | 2011-02-11 (R, EMD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | R2010-47 EMD2010-148 Link to ES Tech. Rep. Archives: EMD2010-148 |
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| Conference Information | |
| Committee | EMD R |
| Conference Date | 2011-02-18 - 2011-02-18 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Shizuoka Univ. (Hamamatsu) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | R |
| Conference Code | 2011-02-EMD-R |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Logic stabilization of unstable logic circuit with open fault |
| Sub Title (in English) | |
| Keyword(1) | Floating gate fault |
| Keyword(2) | Stabilized logic value |
| Keyword(3) | Laser irradiation |
| Keyword(4) | Inverter circuit |
| Keyword(5) | Middle voltage |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Taiki Yasutomi |
| 1st Author's Affiliation | Kochi University of Technology (KUT) |
| 2nd Author's Name | Masaru Sanada |
| 2nd Author's Affiliation | Kochi University of Technology (KUT) |
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| Speaker | Author-1 |
| Date Time | 2011-02-18 15:25:00 |
| Presentation Time | 25 minutes |
| Registration for | R |
| Paper # | R2010-47, EMD2010-148 |
| Volume (vol) | vol.110 |
| Number (no) | no.415(R), no.416(EMD) |
| Page | pp.31-36 |
| #Pages | 6 |
| Date of Issue | 2011-02-11 (R, EMD) |
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