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| Presentation | 2011-02-14 14:10 A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.)  DC2010-65 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Some large-scale integrated circuits have been recently designed at high-level by behavioral descriptions. Behavioral synthesis can transform behavioral descriptions to register transfer level circuits that consist of a controller and a datapath. In this paper, we propose a test generation method for datapath circuits using functional time expansion models which are defined as time expansion models with functional information such as latency, and the input sequence for control signal lines and the output sequence for status signal lines of datapaths. We also propose two types of functional time expansion model generation methods. One is generated from controllers and the other is generated from functional verification patterns. Experimental results for practical circuits show that the proposed test generation methods increase fault coverage by 14.98% on the average and accelerate test generation time by 81.29 times on the average. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | n-state transition cover / functional time expansion models / datapath circuits / constrained sequential test generation / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 413, DC2010-65, pp. 39-44, Feb. 2011. | |
| Paper # | DC2010-65 | |
| Date of Issue | 2011-02-07 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2010-65 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2011-02-14 - 2011-02-14 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2011-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models |
| Sub Title (in English) | |
| Keyword(1) | n-state transition cover |
| Keyword(2) | functional time expansion models |
| Keyword(3) | datapath circuits |
| Keyword(4) | constrained sequential test generation |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Teppei Hayakawa |
| 1st Author's Affiliation | Nihon University (Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University (Nihon Univ.) |
| 3rd Author's Name | Masayoshi Yoshimura |
| 3rd Author's Affiliation | Kyushu University (Kyushu Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-02-14 14:10:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2010-65 |
| Volume (vol) | vol.110 |
| Number (no) | no.413 |
| Page | pp.39-44 |
| #Pages | 6 |
| Date of Issue | 2011-02-07 (DC) |
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