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Paper Abstract and Keywords
Presentation 2011-02-14 16:05
Note on Area Overhead Reduction for Reconfigurable On-Chip Debug Circui
Masayuki Arai, Yoshihiro Tabata, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2010-69
Abstract (in Japanese) (See Japanese page) 
(in English) In this study we evaluate the effectiveness of a reconfigurable on-chip debug circuit, in terms of hardware overhead and detection capability of bugs. For target circuit under debug, we apply a 32-bit RISC microcontroller, SH3-DSP, , and evaluate the hardware overhead of design-for-debug circuit. The evaluation result changing the arrangement of debug circuit indicates that the hardware overhead of debug circuit against the target circuit was in the range of 0.1% to 3.2%. Next, we evaluate whether a fault effect can be observed or not by using debug circuit. On the target processor circuit we inject 40 different faults and checked whether a fault is observed at each observation point in the processor core, measuring the number of clock cycles required for observation. We also evaluated the rate of observability of each fault.
Keyword (in Japanese) (See Japanese page) 
(in English) on-chip debug / silicon debug / post-silicon validation / design-for-debug / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 413, DC2010-69, pp. 63-68, Feb. 2011.
Paper # DC2010-69 
Date of Issue 2011-02-07 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2011-02-14 - 2011-02-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2011-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Note on Area Overhead Reduction for Reconfigurable On-Chip Debug Circui 
Sub Title (in English)  
Keyword(1) on-chip debug  
Keyword(2) silicon debug  
Keyword(3) post-silicon validation  
Keyword(4) design-for-debug  
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1st Author's Name Masayuki Arai  
1st Author's Affiliation Tokyo Metropolitan University (Tokyo Metro. Univ.)
2nd Author's Name Yoshihiro Tabata  
2nd Author's Affiliation Tokyo Metropolitan University (Tokyo Metro. Univ.)
3rd Author's Name Kazuhiko Iwasaki  
3rd Author's Affiliation Tokyo Metropolitan University (Tokyo Metro. Univ.)
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Speaker Author-2 
Date Time 2011-02-14 16:05:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2010-69 
Volume (vol) vol.110 
Number (no) no.413 
Page pp.63-68 
#Pages
Date of Issue 2011-02-07 (DC) 


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