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Paper Abstract and Keywords
Presentation 2011-01-25 14:10
A design of FPGA routing structure with Switch-Block-cum-Shifter
Komei Yoshizawa, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CAS2010-88
Abstract (in Japanese) (See Japanese page) 
(in English) In conventional FPGA(Field Programmable Gate Array), programmable innterconects have great impacts on delay and area. They cause the degradation of device performance. One of the reasons is a detour of signal
propagation route. Because of this, routing delay and area are increased. In order to mitigate detours, we propose the Switch-Block-cum-Shifter. In this paper, we design Switch Blocks with e-Shuttle 65nm library and evaluate
them. As a result, the area increase 14.8%. It also decreases delay and resolves detours on the detour of signal propagation route.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / routing architecture / Switch Block / shifter / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 389, CAS2010-88, pp. 23-28, Jan. 2011.
Paper # CAS2010-88 
Date of Issue 2011-01-18 (CAS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CAS  
Conference Date 2011-01-25 - 2011-01-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumamoto University 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CAS 
Conference Code 2011-01-CAS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A design of FPGA routing structure with Switch-Block-cum-Shifter 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) routing architecture  
Keyword(3) Switch Block  
Keyword(4) shifter  
1st Author's Name Komei Yoshizawa  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Kazuki Inoue  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Motoki Amagasaki  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Toshinori Sueyoshi  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Date Time 2011-01-25 14:10:00 
Presentation Time 25 
Registration for CAS 
Paper # IEICE-CAS2010-88 
Volume (vol) IEICE-110 
Number (no) no.389 
Page pp.23-28 
#Pages IEICE-6 
Date of Issue IEICE-CAS-2011-01-18 

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