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Presentation 2011-01-20 14:20
[Invited Talk] CMOS Hyper-Miniaturization and Cooperation with 3D System Design Integration
Kazuya Okamoto, Ryohei Satoh (Osaka Univ.) Link to ES Tech. Rep. Archives: ICD2010-131
Abstract (in Japanese) (See Japanese page) 
(in English) Miniaturization technology based on Dennard’s rule for CMOS devices has been progressing technically over time and has conferred a benefit on the life of mankind. Lithography has made amazing progress so far, achieving high resolution at 32nm-L/S or below using 193nm-UV light. However, there is a low probability that this scenario of producing ever-finer feature geometry will continue, because resolution capabilities will possibly reach a critical limit due to CMOS performance threshold and chip economy. Therefore, to assure continued performance improvements and to create added-value by miniaturization for the future devices, a new 3 dimensional (3D) monolithic integration should acquire increased importance. Especially, precision wafer-to-wafer (W2W) bonding using through-Si-via (TSV) interconnect would be an integral part of this technology. This paper describes key issues of the precision W2W bonding and the inspection methodology to meet higher alignment accuracy. Furthermore, a new system design methodology is described. In conclusion, W2W-3D integration with the new system integrated design will be crucial for the miniaturization-life extension and would be incorporated into the future CMOS devices in a practical manner.
Keyword (in Japanese) (See Japanese page) 
(in English) Miniaturization / 3D integration / TSV / Wafer bonding / Inspection / System design integration / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 380, ICD2010-131, pp. 29-29, Jan. 2011.
Paper # ICD2010-131 
Date of Issue 2011-01-13 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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Download PDF Link to ES Tech. Rep. Archives: ICD2010-131

Conference Information
Committee ICD IPSJ-ARC  
Conference Date 2011-01-20 - 2011-01-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio University (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2011-01-ICD-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) CMOS Hyper-Miniaturization and Cooperation with 3D System Design Integration 
Sub Title (in English)  
Keyword(1) Miniaturization  
Keyword(2) 3D integration  
Keyword(3) TSV  
Keyword(4) Wafer bonding  
Keyword(5) Inspection  
Keyword(6) System design integration  
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Keyword(8)  
1st Author's Name Kazuya Okamoto  
1st Author's Affiliation Osaka University (Osaka Univ.)
2nd Author's Name Ryohei Satoh  
2nd Author's Affiliation Osaka University (Osaka Univ.)
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Speaker Author-1 
Date Time 2011-01-20 14:20:00 
Presentation Time 50 minutes 
Registration for ICD 
Paper # ICD2010-131 
Volume (vol) vol.110 
Number (no) no.380 
Page p.29 
#Pages
Date of Issue 2011-01-13 (ICD) 


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