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| Presentation | 2011-01-18 10:55 Feasibility of JHDL for Dynamically Reconfigurable Hardware Design Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.)  VLD2010-103 CPSY2010-58 RECONF2010-72 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | To develop applications for dynamically reconfigurable hardware, the description language which increases the efficiency of the design and the design environment which enables the performance evaluation at the high abstraction level are important. JHDL (Just-another Hardware Description Language) developed and distributed by BYU (Brigham Young University) is one of such a design environment. JHDL is implemented as a class library of the Java programming language, and it enables hardware design using Java. JHDL has been developed mainly for FPGA (Field Programmable Gate Array) design, therefore only techniques for partial reconfigurations are proposed for dynamically reconfigurable systems. So, in this paper, we investigated the feasibility of JHDL for designing various dynamically reconfigurable systems. Based on the partial reconfiguration technique using PRSocket proposed by BYU, the description techniques and functions required for various dynamically reconfigurable systems are clarified. Moreover, we propose the extensions for JHDL which can increase the efficiency of the design more. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Dynamically reconfigurable hardware / Hardware description language / Design environment / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 362, RECONF2010-72, pp. 133-138, Jan. 2011. | |
| Paper # | RECONF2010-72 | |
| Date of Issue | 2011-01-10 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2010-103 CPSY2010-58 RECONF2010-72 |
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| Conference Information | |
| Committee | RECONF VLD CPSY IPSJ-SLDM |
| Conference Date | 2011-01-17 - 2011-01-18 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Keio Univ (Hiyoshi Campus) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2011-01-RECONF-VLD-CPSY-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Feasibility of JHDL for Dynamically Reconfigurable Hardware Design |
| Sub Title (in English) | |
| Keyword(1) | Dynamically reconfigurable hardware |
| Keyword(2) | Hardware description language |
| Keyword(3) | Design environment |
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| 1st Author's Name | Naomichi Furushima |
| 1st Author's Affiliation | Okayama University (Okayama Univ.) |
| 2nd Author's Name | Nobuya Watanabe |
| 2nd Author's Affiliation | Okayama University (Okayama Univ.) |
| 3rd Author's Name | Akira Nagoya |
| 3rd Author's Affiliation | Okayama University (Okayama Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-01-18 10:55:00 |
| Presentation Time | 20 minutes |
| Registration for | RECONF |
| Paper # | VLD2010-103, CPSY2010-58, RECONF2010-72 |
| Volume (vol) | vol.110 |
| Number (no) | no.360(VLD), no.361(CPSY), no.362(RECONF) |
| Page | pp.133-138 |
| #Pages | 6 |
| Date of Issue | 2011-01-10 (VLD, CPSY, RECONF) |
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