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Paper Abstract and Keywords
Presentation 2011-01-18 11:15
Optimization of Local Routing Networks in a Logic Block for Cluster Based FPGAs
Yuji Masumitsu, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2010-104 CPSY2010-59 RECONF2010-73
Abstract (in Japanese) (See Japanese page) 
(in English) Feild programmable gate arrays (FPGAs) are mostly cluseter-based FPGAs. In a cluster-based FPGA, a logic block consists some look-up tables (LUTs) and local routing networks. The LUT inputs can be chosen from two sources: logic block inputs and feedback connections, which are the outputs of LUTs in this logic block. However, the local routing networks have huge wires and obtained major area on FPGA. Thus, it is important to improve local routing networks for cluster-based FPGA. In this paper, we propose local routing network structure to minimize FPGA area. As a result, the average of FPGA area is decreased by 17.3\% as compared with conventional local routing networks.
Keyword (in Japanese) (See Japanese page) 
(in English) cluster-based FPGA / local routing networks / logic clusters / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 362, RECONF2010-73, pp. 139-144, Jan. 2011.
Paper # RECONF2010-73 
Date of Issue 2011-01-10 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
技術研究報告に掲載された論文の著作権はIEICEに帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-104 CPSY2010-59 RECONF2010-73

Conference Information
Committee RECONF VLD CPSY IPSJ-SLDM  
Conference Date 2011-01-17 - 2011-01-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2011-01-RECONF-VLD-CPSY-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Optimization of Local Routing Networks in a Logic Block for Cluster Based FPGAs 
Sub Title (in English)  
Keyword(1) cluster-based FPGA  
Keyword(2) local routing networks  
Keyword(3) logic clusters  
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1st Author's Name Yuji Masumitsu  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Motoki Amagasaki  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Masahiro Iida  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Toshinori Sueyoshi  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker
Date Time 2011-01-18 11:15:00 
Presentation Time 20 
Registration for RECONF 
Paper # IEICE-VLD2010-104,IEICE-CPSY2010-59,IEICE-RECONF2010-73 
Volume (vol) IEICE-110 
Number (no) no.360(VLD), no.361(CPSY), no.362(RECONF) 
Page pp.139-144 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2011-01-10,IEICE-CPSY-2011-01-10,IEICE-RECONF-2011-01-10 


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