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| Presentation | 2011-01-18 15:10 Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications)  VLD2010-110 CPSY2010-65 RECONF2010-79 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Battery driven multi-media applications require both high performance and energy efficiency. Recon-figurable accelerators with a lot of processing elements are hopeful approach. SLD(Silent Large Datapath)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 PEs without registers and a small micro-controller for data memory access. It was fabricated in 2.1mm × 4.2mm 65 nm CMOS, and achieves 1.356GOPS/11mW sustained performance by reducing overhead of clock tree and the benefit of voltage scaling. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Reconfigurable System / Low Power Design / 65nmCMOS / Real Chip Evaluation / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 362, RECONF2010-79, pp. 175-180, Jan. 2011. | |
| Paper # | RECONF2010-79 | |
| Date of Issue | 2011-01-10 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2010-110 CPSY2010-65 RECONF2010-79 |
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| Conference Information | |
| Committee | RECONF VLD CPSY IPSJ-SLDM |
| Conference Date | 2011-01-17 - 2011-01-18 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Keio Univ (Hiyoshi Campus) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2011-01-RECONF-VLD-CPSY-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater |
| Sub Title (in English) | |
| Keyword(1) | Reconfigurable System |
| Keyword(2) | Low Power Design |
| Keyword(3) | 65nmCMOS |
| Keyword(4) | Real Chip Evaluation |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Nobuaki Ozaki |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Yoshihiro Yasuda |
| 2nd Author's Affiliation | Keio University (Keio Univ.) |
| 3rd Author's Name | Yoshiki Saito |
| 3rd Author's Affiliation | Keio University (Keio Univ.) |
| 4th Author's Name | Daisuke Ikebuchi |
| 4th Author's Affiliation | Keio University (Keio Univ.) |
| 5th Author's Name | Masayuki Kimura |
| 5th Author's Affiliation | Keio University (Keio Univ.) |
| 6th Author's Name | Hideharu Amano |
| 6th Author's Affiliation | Keio University (Keio Univ.) |
| 7th Author's Name | Hiroshi Nakamura |
| 7th Author's Affiliation | University of Tokyo (Univ. of Tokyo) |
| 8th Author's Name | Kimiyoshi Usami |
| 8th Author's Affiliation | Shibaura Institute of Technology (Shibaura Inst. Tech.) |
| 9th Author's Name | Mitaro Namiki |
| 9th Author's Affiliation | Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.) |
| 10th Author's Name | Masaaki Kondo |
| 10th Author's Affiliation | The University of Electro-Communications (Univ. of Electro-Communications) |
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| Speaker | Author-1 |
| Date Time | 2011-01-18 15:10:00 |
| Presentation Time | 20 minutes |
| Registration for | RECONF |
| Paper # | VLD2010-110, CPSY2010-65, RECONF2010-79 |
| Volume (vol) | vol.110 |
| Number (no) | no.360(VLD), no.361(CPSY), no.362(RECONF) |
| Page | pp.175-180 |
| #Pages | 6 |
| Date of Issue | 2011-01-10 (VLD, CPSY, RECONF) |
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