IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2011-01-17 12:05
Parallelization of the channel width search for FPGA routing
Hiroomi Sawada, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto) VLD2010-89 CPSY2010-44 RECONF2010-58
Abstract (in Japanese) (See Japanese page) 
(in English) As the FPGA becomes resourceful, the design time becomes longer.
Especially, routing process occupies the large portion of
it, because the routing patterns increase substantially with
FPGA's growing.
Therefore, we propose the parallelizing algorithm for FPGA's
channel width search in order to reduce the automated design
time.
This algorithm doesn't lose the routing cost, because each
channel width search are independent with respect to one
another.
As a result, we achieved speed-up 5.30 times highest, 1.90 times the rate improvement on the average without
cost deterioration.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA routing / parallel algorithm / cluster computer / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 361, CPSY2010-44, pp. 31-36, Jan. 2011.
Paper # CPSY2010-44 
Date of Issue 2011-01-10 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
技術研究報告に掲載された論文の著作権はIEICEに帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-89 CPSY2010-44 RECONF2010-58

Conference Information
Committee RECONF VLD CPSY IPSJ-SLDM  
Conference Date 2011-01-17 - 2011-01-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To CPSY 
Conference Code 2011-01-RECONF-VLD-CPSY-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Parallelization of the channel width search for FPGA routing 
Sub Title (in English)  
Keyword(1) FPGA routing  
Keyword(2) parallel algorithm  
Keyword(3) cluster computer  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroomi Sawada  
1st Author's Affiliation Kumamoto University (Kumamoto)
2nd Author's Name Morihiro Kuga  
2nd Author's Affiliation Kumamoto University (Kumamoto)
3rd Author's Name Toshinori Sueyoshi  
3rd Author's Affiliation Kumamoto University (Kumamoto)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker
Date Time 2011-01-17 12:05:00 
Presentation Time 20 
Registration for CPSY 
Paper # IEICE-VLD2010-89,IEICE-CPSY2010-44,IEICE-RECONF2010-58 
Volume (vol) IEICE-110 
Number (no) no.360(VLD), no.361(CPSY), no.362(RECONF) 
Page pp.31-36 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2011-01-10,IEICE-CPSY-2011-01-10,IEICE-RECONF-2011-01-10 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan