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| Presentation | 2011-01-17 12:05 Parallelization of the channel width search for FPGA routing Hiroomi Sawada, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto)  VLD2010-89 CPSY2010-44 RECONF2010-58 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | As the FPGA becomes resourceful, the design time becomes longer. Especially, routing process occupies the large portion of it, because the routing patterns increase substantially with FPGA's growing. Therefore, we propose the parallelizing algorithm for FPGA's channel width search in order to reduce the automated design time. This algorithm doesn't lose the routing cost, because each channel width search are independent with respect to one another. As a result, we achieved speed-up 5.30 times highest, 1.90 times the rate improvement on the average without cost deterioration. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA routing / parallel algorithm / cluster computer / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 361, CPSY2010-44, pp. 31-36, Jan. 2011. | |
| Paper # | CPSY2010-44 | |
| Date of Issue | 2011-01-10 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2010-89 CPSY2010-44 RECONF2010-58 |
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| Conference Information | |
| Committee | RECONF VLD CPSY IPSJ-SLDM |
| Conference Date | 2011-01-17 - 2011-01-18 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Keio Univ (Hiyoshi Campus) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2011-01-RECONF-VLD-CPSY-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Parallelization of the channel width search for FPGA routing |
| Sub Title (in English) | |
| Keyword(1) | FPGA routing |
| Keyword(2) | parallel algorithm |
| Keyword(3) | cluster computer |
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| 1st Author's Name | Hiroomi Sawada |
| 1st Author's Affiliation | Kumamoto University (Kumamoto) |
| 2nd Author's Name | Morihiro Kuga |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto) |
| 3rd Author's Name | Toshinori Sueyoshi |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto) |
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| Speaker | Author-1 |
| Date Time | 2011-01-17 12:05:00 |
| Presentation Time | 20 minutes |
| Registration for | CPSY |
| Paper # | VLD2010-89, CPSY2010-44, RECONF2010-58 |
| Volume (vol) | vol.110 |
| Number (no) | no.360(VLD), no.361(CPSY), no.362(RECONF) |
| Page | pp.31-36 |
| #Pages | 6 |
| Date of Issue | 2011-01-10 (VLD, CPSY, RECONF) |
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