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Paper Abstract and Keywords
Presentation 2011-01-17 14:10
Power reduction in Dynamically Reconfigurable Processor by Dynamically VDD Switching and a mapping technique to reduce energy overhead
Tatsuya Yamamoto (Shibaura Institute), Kazuei Hironaka (Keio Univ.), Yuki Hayakawa (Shibaura Institute), Masayuki Kimura, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Institute) VLD2010-92 CPSY2010-47 RECONF2010-61
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Processors. Either high or low supply is dynamically selected at each PE at the context-by-context basis. We designed a part of a PE array and applied this technique. A test chip fabricated in 65nm technology operated successfully. Detailed simulations revealed that energy reduction is hindered by energy overhead due to supply switching when we use even lower VDD. We propose a mapping optimization algorithm “PFCM” to minimize the overhead. PFCM reduced energy overhead by 87% and thereby the dynamic VDD switching technique reduced energy dissipation by up to 12%.
Keyword (in Japanese) (See Japanese page) 
(in English) Dynamically Reconfigurable Processor / Power Reduction / Dynamic VDD Swiching / Mapping Optimization / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 360, VLD2010-92, pp. 49-54, Jan. 2011.
Paper # VLD2010-92 
Date of Issue 2011-01-10 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-92 CPSY2010-47 RECONF2010-61

Conference Information
Conference Date 2011-01-17 - 2011-01-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2011-01-RECONF-VLD-CPSY-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Power reduction in Dynamically Reconfigurable Processor by Dynamically VDD Switching and a mapping technique to reduce energy overhead 
Sub Title (in English)  
Keyword(1) Dynamically Reconfigurable Processor  
Keyword(2) Power Reduction  
Keyword(3) Dynamic VDD Swiching  
Keyword(4) Mapping Optimization  
1st Author's Name Tatsuya Yamamoto  
1st Author's Affiliation Shibaura Institute of Technology (Shibaura Institute)
2nd Author's Name Kazuei Hironaka  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Yuki Hayakawa  
3rd Author's Affiliation Shibaura Institute of Technology (Shibaura Institute)
4th Author's Name Masayuki Kimura  
4th Author's Affiliation Keio University (Keio Univ.)
5th Author's Name Hideharu Amano  
5th Author's Affiliation Keio University (Keio Univ.)
6th Author's Name Kimiyoshi Usami  
6th Author's Affiliation Shibaura Institute of Technology (Shibaura Institute)
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Date Time 2011-01-17 14:10:00 
Presentation Time 20 
Registration for VLD 
Paper # IEICE-VLD2010-92,IEICE-CPSY2010-47,IEICE-RECONF2010-61 
Volume (vol) IEICE-110 
Number (no) no.360(VLD), no.361(CPSY), no.362(RECONF) 
Page pp.49-54 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2011-01-10,IEICE-CPSY-2011-01-10,IEICE-RECONF-2011-01-10 

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