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Paper Abstract and Keywords
Presentation 2011-01-17 13:30
Approximated Variable Scheduling for High-Level Synthesis
Kousuke Sone, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2010-90 CPSY2010-45 RECONF2010-59
Abstract (in Japanese) (See Japanese page) 
(in English) This article presents approximated variable scheduling methods for high-level synthesis. In the presence of indefinite cycle operations, which complete their tasks in different cycles depending on the values of their operands, conventional static scheduling often results in inefficient execution. \textit{Variable scheduling} enables efficient computation by adjusting the execution steps of each operation dynamically based on the completion signal from the functional unit. However, the size of the state transition graphs, which are the results of variable scheduling, often grow so large that the area and the delay of the synthesized circuits may not be acceptable. For the purpose of relaxing this problem, we propose two approximate methods which curve the area and the delay of the synthesized circuits at the cost of the average execution cycles in variable scheduling. The first method is based on deletion of the states that do not contribute to the reduction of the execution cycles. The second one is based on state independent binding of operations to functional units, which reduces both the state transition graph size and the datapath complexity. Experimental results show that the size and the delay of the circuits are reduced as compared with the conventional variable scheduling, although the average number of execution cycles is increased.
Keyword (in Japanese) (See Japanese page) 
(in English) high-level synthesis / indefinite cycle operation / variable scheduling / approximate method / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 360, VLD2010-90, pp. 37-42, Jan. 2011.
Paper # VLD2010-90 
Date of Issue 2011-01-10 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Download PDF VLD2010-90 CPSY2010-45 RECONF2010-59

Conference Information
Conference Date 2011-01-17 - 2011-01-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2011-01-RECONF-VLD-CPSY-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Approximated Variable Scheduling for High-Level Synthesis 
Sub Title (in English)  
Keyword(1) high-level synthesis  
Keyword(2) indefinite cycle operation  
Keyword(3) variable scheduling  
Keyword(4) approximate method  
1st Author's Name Kousuke Sone  
1st Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
2nd Author's Name Nagisa Ishiura  
2nd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
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Date Time 2011-01-17 13:30:00 
Presentation Time 20 
Registration for VLD 
Paper # IEICE-VLD2010-90,IEICE-CPSY2010-45,IEICE-RECONF2010-59 
Volume (vol) IEICE-110 
Number (no) no.360(VLD), no.361(CPSY), no.362(RECONF) 
Page pp.37-42 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2011-01-10,IEICE-CPSY-2011-01-10,IEICE-RECONF-2011-01-10 

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