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| Presentation | 2010-12-16 15:10 [Poster Presentation] Design of An FU Network for Array Accelerators Suguru Ooue, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST)  ICD2010-115 Link to ES Tech. Rep. Archives: ICD2010-115 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We have proposed Linear Array Pipeline Processor (LAPP) as a special implementation of Function Unit (FU) array based accelerator. Its VLIW processor as the front-end part and the unmapped FU can be power-gated to ensure an energy-efficiency design, running well mapped conventional VLIW instructions. In this poster, we will introduce an FU network design for LAPP, which traces register numbers appearing in mapped instructions and then propagates minimum necessary register values to successive array stages. According to an HDL implementation, the delay time of the selector is 5.74 FO4. The result shows that the selectors will not extend any critical path in LAPP. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | array execution units / VLIW / FU Network / instruction mapping / reconfigurable architecture / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 344, ICD2010-115, pp. 97-99, Dec. 2010. | |
| Paper # | ICD2010-115 | |
| Date of Issue | 2010-12-09 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2010-115 Link to ES Tech. Rep. Archives: ICD2010-115 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2010-12-16 - 2010-12-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | RCAST, Univ. of Tokyo |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Workshop for Graduate Student and Young Researchers |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2010-12-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of An FU Network for Array Accelerators |
| Sub Title (in English) | |
| Keyword(1) | array execution units |
| Keyword(2) | VLIW |
| Keyword(3) | FU Network |
| Keyword(4) | instruction mapping |
| Keyword(5) | reconfigurable architecture |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Suguru Ooue |
| 1st Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 2nd Author's Name | Takuya Iwakami |
| 2nd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 3rd Author's Name | Kazuhiro Yoshimura |
| 3rd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 4th Author's Name | Takashi Nakada |
| 4th Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 5th Author's Name | Yasuhiko Nakashima |
| 5th Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
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| Speaker | Author-1 |
| Date Time | 2010-12-16 15:10:00 |
| Presentation Time | 120 minutes |
| Registration for | ICD |
| Paper # | ICD2010-115 |
| Volume (vol) | vol.110 |
| Number (no) | no.344 |
| Page | pp.97-99 |
| #Pages | 3 |
| Date of Issue | 2010-12-09 (ICD) |
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