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Paper Abstract and Keywords
Presentation 2010-12-03 10:25
Networked hw/sw complex system and virtual hardware circuit of video codec
Hakaru Tamukoh, Masahiro Ariizumi, Nadav Bergstein, Masatoshi Sekine (TUAT) SIS2010-49
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we describe a design example of a networked hw/sw complex system based on the hardware object model.
In the networked hw/sw complex system, a virtual hardware circuit is downloaded via network and is realized into an FPGA.
By implementing the virtual hardware circuit as the processing unit that executes a very large scale computing, we can develop high-performance hw/sw complex system which processes both of the speed of hardware and the flexibility of software.
In this paper, we develop two types of wavelet transfer based video codec to evaluate the networked hw/sw complex system.
Experimental results show that the proposed virtual hardware video codec is 25 times faster than the software implementation.
Besides, we succeed of downloading, remotely operating and realization of the virtual hardware circuit.
Keyword (in Japanese) (See Japanese page) 
(in English) networked hw/sw complex system / object oriented design / FPGA / digital hardware / video codec / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 322, SIS2010-49, pp. 83-88, Dec. 2010.
Paper # SIS2010-49 
Date of Issue 2010-11-25 (SIS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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Conference Information
Committee SIS  
Conference Date 2010-12-02 - 2010-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SIS 
Conference Code 2010-12-SIS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Networked hw/sw complex system and virtual hardware circuit of video codec 
Sub Title (in English)  
Keyword(1) networked hw/sw complex system  
Keyword(2) object oriented design  
Keyword(3) FPGA  
Keyword(4) digital hardware  
Keyword(5) video codec  
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1st Author's Name Hakaru Tamukoh  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Masahiro Ariizumi  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name Nadav Bergstein  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
4th Author's Name Masatoshi Sekine  
4th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
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Speaker Author-1 
Date Time 2010-12-03 10:25:00 
Presentation Time 25 minutes 
Registration for SIS 
Paper # SIS2010-49 
Volume (vol) vol.110 
Number (no) no.322 
Page pp.83-88 
#Pages
Date of Issue 2010-11-25 (SIS) 


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