Paper Abstract and Keywords |
Presentation |
2010-12-02 15:15
Circuit Design of a 128-point FFT Processor Using Pipeline MDC Architecture for 8x8 MIMO-OFDM Receivers Atsushi Orikasa, Yoshikazu Miyanaga, Shingo Yoshizawa (Hokkaido Univ.) SIS2010-45 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This report presents a VLSI architecture of 128-point FFT in a 8x8 MIMO-OFDM receiver. A pipeline FFT processor based on multi-path delay commutator(MDC) architecture is effective for 4x4 MIMO-OFDM systems. To achieve the communication of more high speed and large capacity, it is necessary to design the FFT processor corresponding to the MIMO-OFDM receiver that increases the number of streams. In this paper, we propose the FFT processor to apply the MDC architecture for 8x8 MIMO-OFDM systems. The proposed FFT processor uses the pre- and post-commutators instead of delay elements and improves area and power efficiency. The designed circuit has been implemented to a 90-nm CMOS process and evaluated in circuit area and power consumption. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FFT / Multi-path delay commutator(MDC) / MIMO-OFDM / VLSI Architecture / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 322, SIS2010-45, pp. 59-64, Dec. 2010. |
Paper # |
SIS2010-45 |
Date of Issue |
2010-11-25 (SIS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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SIS2010-45 |
Conference Information |
Committee |
SIS |
Conference Date |
2010-12-02 - 2010-12-03 |
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(See Japanese page) |
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Paper Information |
Registration To |
SIS |
Conference Code |
2010-12-SIS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Circuit Design of a 128-point FFT Processor Using Pipeline MDC Architecture for 8x8 MIMO-OFDM Receivers |
Sub Title (in English) |
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Keyword(1) |
FFT |
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Multi-path delay commutator(MDC) |
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MIMO-OFDM |
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VLSI Architecture |
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1st Author's Name |
Atsushi Orikasa |
1st Author's Affiliation |
Hokkaido University (Hokkaido Univ.) |
2nd Author's Name |
Yoshikazu Miyanaga |
2nd Author's Affiliation |
Hokkaido University (Hokkaido Univ.) |
3rd Author's Name |
Shingo Yoshizawa |
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Hokkaido University (Hokkaido Univ.) |
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Speaker |
Author-1 |
Date Time |
2010-12-02 15:15:00 |
Presentation Time |
20 minutes |
Registration for |
SIS |
Paper # |
SIS2010-45 |
Volume (vol) |
vol.110 |
Number (no) |
no.322 |
Page |
pp.59-64 |
#Pages |
6 |
Date of Issue |
2010-11-25 (SIS) |