IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-12-01 09:50
Fabrication in Low Power Process and Evaluation of Power Reconfigurable Field Programmable Gate Array
Masakazu Hioki (AIST), Takashi Kawanami (KIT), Yohei Matsumoto (TUMSAT), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) RECONF2010-45
Abstract (in Japanese) (See Japanese page) 
(in English) Flex Power FPGA that is FPGA with power reconfigurability aims at the reduction of static power. The reduction of off current in which the static power originates in Flex Power FPGA depends on both the variation width of an off current of MOSFET when the body bias voltage is applied and the fraction of MOSFET with low threshold voltage in a circuit. In the recent years, two or more fabrication processes are prepared in a technology node to satisfy the severe demands on the operational specifications such as a faster operating frequency and lower power consumption in the various target applications. In addition, two or more kinds of MOSFET with a different characteristic exist in each process and the integrated circuit can be designed by selectively using these MOSFETs. And, the behavior of the change in an off current when the body bias voltage is applied to these MOSFETs is different respectively. In this paper, Flex Power FPGA is fabricated by the low power 90nm CMOS process where the variation width of an off current by the applying of the body bias voltage is larger and the off current reduction is evaluated.
Keyword (in Japanese) (See Japanese page) 
(in English) Flex Power FPGA / Off current / Low power process / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 319, RECONF2010-45, pp. 37-42, Nov. 2010.
Paper # RECONF2010-45 
Date of Issue 2010-11-23 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2010-45

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2010-11-29 - 2010-12-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 ―New Field of VLSI Design― 
Paper Information
Registration To RECONF 
Conference Code 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fabrication in Low Power Process and Evaluation of Power Reconfigurable Field Programmable Gate Array 
Sub Title (in English)  
Keyword(1) Flex Power FPGA  
Keyword(2) Off current  
Keyword(3) Low power process  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Masakazu Hioki  
1st Author's Affiliation National Institute of Advanced Science and Technology (AIST)
2nd Author's Name Takashi Kawanami  
2nd Author's Affiliation Kanazawa Institute of Technology (KIT)
3rd Author's Name Yohei Matsumoto  
3rd Author's Affiliation Tokyo University of Marine Science and Technology (TUMSAT)
4th Author's Name Toshiyuki Tsutsumi  
4th Author's Affiliation Meiji University (Meiji Univ.)
5th Author's Name Tadashi Nakagawa  
5th Author's Affiliation National Institute of Advanced Science and Technology (AIST)
6th Author's Name Toshihiro Sekigawa  
6th Author's Affiliation National Institute of Advanced Science and Technology (AIST)
7th Author's Name Hanpei Koike  
7th Author's Affiliation National Institute of Advanced Science and Technology (AIST)
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker
Date Time 2010-12-01 09:50:00 
Presentation Time 20 
Registration for RECONF 
Paper # IEICE-RECONF2010-45 
Volume (vol) IEICE-110 
Number (no) no.319 
Page pp.37-42 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2010-11-23 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan