IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-12-01 15:10
A proposal for VLSI model for evaluation of rush current by power gating
Hiroto Yamaguchi, Junki Miyajima, Tomohiko Sumi, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.) VLD2010-82 DC2010-49
Abstract (in Japanese) (See Japanese page) 
(in English) Due to the rapid progress of process technologies and variety of uses, the main percentage of total power consumption is switched from dynamic power consumption to static power consumption, so the leakage power is serious problem. The MTCMOS technique can reduce the leak current. This technique has not only positive effects but also the negative effects which are the rush current and so on. To use the MTCMOS technique for LSI need to analyze rush current. Then the paper propose the technique of rush current evaluation environment of the LSI model.
Keyword (in Japanese) (See Japanese page) 
(in English) MTCMOS / rush current / power wiring / centralization / real LSI model / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 316, VLD2010-82, pp. 179-184, Nov. 2010.
Paper # VLD2010-82 
Date of Issue 2010-11-22 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-82 DC2010-49

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2010-11-29 - 2010-12-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 ―New Field of VLSI Design― 
Paper Information
Registration To VLD 
Conference Code 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A proposal for VLSI model for evaluation of rush current by power gating 
Sub Title (in English)  
Keyword(1) MTCMOS  
Keyword(2) rush current  
Keyword(3) power wiring  
Keyword(4) centralization  
Keyword(5) real LSI model  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroto Yamaguchi  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Junki Miyajima  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
3rd Author's Name Tomohiko Sumi  
3rd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
4th Author's Name Masahiro Fukui  
4th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
5th Author's Name Shuji Tsukiyama  
5th Author's Affiliation Chuo University (Chuo Univ.)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker
Date Time 2010-12-01 15:10:00 
Presentation Time 20 
Registration for VLD 
Paper # IEICE-VLD2010-82,IEICE-DC2010-49 
Volume (vol) IEICE-110 
Number (no) no.316(VLD), no.317(DC) 
Page pp.179-184 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2010-11-22,IEICE-DC-2010-11-22 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan