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Paper Abstract and Keywords
Presentation 2010-12-01 09:50
Preliminary Evaluation of Automatic Thread-Level Parallelization using Binary-Level Variable Analysis
Takashi Shiroto, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2010-37
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, the multi-core processors are widely available.
For effective utilization of the performance of multi-core processors, it is necessary to parallelize programs at thread-level,
and to obtain the multithreaded code.
In general, thread-level parallelization require the source code of target program, but the source code are not always available.
Therefore, we have developed an automatic thread-level parallelizing system that translates programs into multithreaded codes at binary-level.
In parallelization, it is necessary to analyze dependence among variables.
However, register-indirect addressing makes it difficult to analyze dependence of memory variables.

In this study, we implement {\itshape binary-level variable analysis} into our automatic thread-level parallelizing system in order to analyze memory variables.
And, we propose a method that can correctly handle the memory dependencies, which cannot be statically analyzed by {\itshape binary-level variable analysis}.
And we evaluate this system by using the binary codes of practical programs.
Keyword (in Japanese) (See Japanese page) 
(in English) multi-core processor / automatic thread-level parallelization / binary-level variable analysis / runtime check of memory access dependence / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 318, CPSY2010-37, pp. 31-36, Nov. 2010.
Paper # CPSY2010-37 
Date of Issue 2010-11-23 (CPSY) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2010-37

Conference Information
Conference Date 2010-11-29 - 2010-12-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 ―New Field of VLSI Design― 
Paper Information
Registration To CPSY 
Conference Code 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Preliminary Evaluation of Automatic Thread-Level Parallelization using Binary-Level Variable Analysis 
Sub Title (in English)  
Keyword(1) multi-core processor  
Keyword(2) automatic thread-level parallelization  
Keyword(3) binary-level variable analysis  
Keyword(4) runtime check of memory access dependence  
1st Author's Name Takashi Shiroto  
1st Author's Affiliation Utsunomiya University (Utsunomiya Univ.)
2nd Author's Name Kanemitsu Ootsu  
2nd Author's Affiliation Utsunomiya University (Utsunomiya Univ.)
3rd Author's Name Takashi Yokota  
3rd Author's Affiliation Utsunomiya University (Utsunomiya Univ.)
4th Author's Name Takanobu Baba  
4th Author's Affiliation Utsunomiya University (Utsunomiya Univ.)
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Date Time 2010-12-01 09:50:00 
Presentation Time 20 
Registration for CPSY 
Paper # IEICE-CPSY2010-37 
Volume (vol) IEICE-110 
Number (no) no.318 
Page pp.31-36 
#Pages IEICE-6 
Date of Issue IEICE-CPSY-2010-11-23 

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