IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-12-01 14:50
Optimal adder architecture in ultra low voltage domain
Nao Konishi, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. Tech.) VLD2010-81 DC2010-48
Abstract (in Japanese) (See Japanese page) 
(in English) Circuit performance is evaluated for several adder architectures with wiring capacitance extracted from layout at 65nm process. The voltage for the minimum energy is 0.3V, and doesn’t change even with the additional wiring capacitance. Optimal adder architecture that gives the minimum energy differs depending on the target delay. KSA is the optimal adder for 0.6ns and shorter delay, CLA is the optimal for less than 1.1ns, and RCA achieves the minimum energy for 1.1ns and longer delay. The best energy performance is RCA.
Keyword (in Japanese) (See Japanese page) 
(in English) Adder / Ultra Low Voltage / Low Power Technique / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 316, VLD2010-81, pp. 173-178, Nov. 2010.
Paper # VLD2010-81 
Date of Issue 2010-11-22 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-81 DC2010-48

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2010-11-29 - 2010-12-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 ―New Field of VLSI Design― 
Paper Information
Registration To VLD 
Conference Code 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Optimal adder architecture in ultra low voltage domain 
Sub Title (in English)  
Keyword(1) Adder  
Keyword(2) Ultra Low Voltage  
Keyword(3) Low Power Technique  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Nao Konishi  
1st Author's Affiliation Shibaura Institute of Technology (Shibaura Inst. Tech.)
2nd Author's Name Masaru Kudo  
2nd Author's Affiliation Shibaura Institute of Technology (Shibaura Inst. Tech.)
3rd Author's Name Kimiyoshi Usami  
3rd Author's Affiliation Shibaura Institute of Technology (Shibaura Inst. Tech.)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker
Date Time 2010-12-01 14:50:00 
Presentation Time 20 
Registration for VLD 
Paper # IEICE-VLD2010-81,IEICE-DC2010-48 
Volume (vol) IEICE-110 
Number (no) no.316(VLD), no.317(DC) 
Page pp.173-178 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2010-11-22,IEICE-DC-2010-11-22 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan