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| Presentation | 2010-12-01 15:30 Sharing of Clock Gating Modules under Multi-Stage Clock Gating Control Xin Man (Waseda Univ.), Takashi Horiyama (Saitama Univ.), Tomoo Kimura, Koji Kai (Panasonic), Shinji Kimura (Waseda Univ.)  VLD2010-83 DC2010-50 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Clock gating is an effective technique to reduce dynamic power consumption for sequential circuits. This paper shows a sharing method of clock gating logic under multi-stage clock gating control. By sharing the clock gating logic, the total activity of registers and clock gating modules can be reduced. The method is implemented based on BDD and is applied to counters and a set of benchmark circuits. There have been found on average 23.0% cost reduction by the proposed multi-stage clock gating generation method. The power estimation using layout data will also be shown. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | dynamic power reduction / automatic clock gating generation / multi-stage clock gating / BDD / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 316, VLD2010-83, pp. 185-190, Nov. 2010. | |
| Paper # | VLD2010-83 | |
| Date of Issue | 2010-11-22 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2010-83 DC2010-50 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2010-11-29 - 2010-12-01 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kyushu University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2010 ―New Field of VLSI Design― |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Sharing of Clock Gating Modules under Multi-Stage Clock Gating Control |
| Sub Title (in English) | |
| Keyword(1) | dynamic power reduction |
| Keyword(2) | automatic clock gating generation |
| Keyword(3) | multi-stage clock gating |
| Keyword(4) | BDD |
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| 1st Author's Name | Xin Man |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Takashi Horiyama |
| 2nd Author's Affiliation | Saitama University (Saitama Univ.) |
| 3rd Author's Name | Tomoo Kimura |
| 3rd Author's Affiliation | R&D Platform Development Center, Panasonic Corporation (Panasonic) |
| 4th Author's Name | Koji Kai |
| 4th Author's Affiliation | R&D Platform Development Center, Panasonic Corporation (Panasonic) |
| 5th Author's Name | Shinji Kimura |
| 5th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | 1 |
| Date Time | 2010-12-01 15:30:00 |
| Presentation Time | 20 |
| Registration for | VLD |
| Paper # | IEICE-VLD2010-83,IEICE-DC2010-50 |
| Volume (vol) | IEICE-110 |
| Number (no) | no.316(VLD), no.317(DC) |
| Page | pp.185-190 |
| #Pages | IEICE-6 |
| Date of Issue | IEICE-VLD-2010-11-22,IEICE-DC-2010-11-22 |
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