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Paper Abstract and Keywords
Presentation 2010-12-01 10:45
An Effective Processing Method for Parallel Loops on FPGA with PCI-Express
Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) RECONF2010-47
Abstract (in Japanese) (See Japanese page) 
(in English) As FPGAs with a PCI-Express Interface appear in the market, the data transter speed between FPGA and other units, such as CPUs and Memories, is increased However, if the HW execution time is longer than the data transfer time, the data transfer is suspended to wait the HW execution. Threrfore, the data transfer speed decreases. In this paper, we propose a ReST which can process a data parallel loop using an FPGA without suspending the data transfer. We present a ReST framework for the ReST, which generates the HW structure of the ReST. As a result of performance evaluation, we show that the ReST structure using the ReST framework performs well in terms of the Hi-speed data transfer and the the HW execution on the FPGA.
Keyword (in Japanese) (See Japanese page) 
(in English) PCI-Express / Impulse C / Data Parallelism / FPGA / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 319, RECONF2010-47, pp. 49-54, Nov. 2010.
Paper # RECONF2010-47 
Date of Issue 2010-11-23 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2010-47

Conference Information
Conference Date 2010-11-29 - 2010-12-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 ―New Field of VLSI Design― 
Paper Information
Registration To RECONF 
Conference Code 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Effective Processing Method for Parallel Loops on FPGA with PCI-Express 
Sub Title (in English)  
Keyword(1) PCI-Express  
Keyword(2) Impulse C  
Keyword(3) Data Parallelism  
Keyword(4) FPGA  
1st Author's Name Koichi Araki  
1st Author's Affiliation Japan Advanced Institute of Science And Technology (JAIST)
2nd Author's Name Yukinori Sato  
2nd Author's Affiliation Japan Advanced Institute of Science And Technology (JAIST)
3rd Author's Name Yasushi Inoguchi  
3rd Author's Affiliation Japan Advanced Institute of Science And Technology (JAIST)
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Date Time 2010-12-01 10:45:00 
Presentation Time 20 
Registration for RECONF 
Paper # IEICE-RECONF2010-47 
Volume (vol) IEICE-110 
Number (no) no.319 
Page pp.49-54 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2010-11-23 

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