Paper Abstract and Keywords |
Presentation |
2010-11-30 09:30
Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-64 DC2010-31 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The number of sets, block size and associativity determine processor's cache configuration. Particularly in embedded systems, cache configuration can be optimized due to the limitation of target applications. For LRU cache replacement policy, Recently, the CRCB approach has been proposed for LRU-based cache configuration simulation, that can calculate cache hit/miss rate accurately and very fast changing the three parameters described above. However many recent processors use FIFO-based caches instead of LRU-based caches. In this paper, we propose a faster cache configuration simulation method for embedded applications that uses FIFO as a cache replacement policy. We first prove several properties for FIFO-based caches and then we propose a simulation method that can process two or more FIFO-based cache configurations with different cache associativity simultaneously. Experimental results show that our proposed method can obtain accurate cache hits/misses and an average of 18% faster than the conventional simulators. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FIFO / cache simulation / cache memory / optimization of the cache structure / embedded systems / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 316, VLD2010-64, pp. 55-60, Nov. 2010. |
Paper # |
VLD2010-64 |
Date of Issue |
2010-11-22 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2010-64 DC2010-31 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2010-11-29 - 2010-12-01 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kyushu University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2010 ―New Field of VLSI Design― |
Paper Information |
Registration To |
VLD |
Conference Code |
2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy |
Sub Title (in English) |
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Keyword(1) |
FIFO |
Keyword(2) |
cache simulation |
Keyword(3) |
cache memory |
Keyword(4) |
optimization of the cache structure |
Keyword(5) |
embedded systems |
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1st Author's Name |
Masashi Tawada |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Masao Yanagisawa |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Tatsuo Ohtsuki |
3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
4th Author's Name |
Nozomu Togawa |
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Waseda University (Waseda Univ.) |
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Speaker |
1 |
Date Time |
2010-11-30 09:30:00 |
Presentation Time |
20 |
Registration for |
VLD |
Paper # |
IEICE-VLD2010-64,IEICE-DC2010-31 |
Volume (vol) |
IEICE-110 |
Number (no) |
no.316(VLD), no.317(DC) |
Page |
pp.55-60 |
#Pages |
IEICE-6 |
Date of Issue |
IEICE-VLD-2010-11-22,IEICE-DC-2010-11-22 |
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