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| Presentation | 2010-11-29 10:40 Evaluation of frequency components of power noise in CMOS digital LSI Kumpei Yoshikawa, Hiroshi Matsumoto, Yuta Sasaki (Kobe Univ.), Makoto Nagata (Kobe Univ./CREST-JST)  CPM2010-124 ICD2010-83 Link to ES Tech. Rep. Archives: CPM2010-124 ICD2010-83 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recent trends of electric devices are higher performance and/or lower power consumption. To achieve these designs, LSI chips that mounted on electric devices become larger-size, high-integrated and lower supply voltage. As a results, an increasing density of current inside LSI and a degradation of noise margin cause power-supply noise induced problems such as Power Integrity (PI) and Signal Integrity (SI). This paper proposes a evaluation of frequency components of power noise in processor. On-chip power noise and On-board power noise are measured, and frequency component of these noise are evaluated. Charging capacitance model are also evaluated and confirmed the accuracy of the model. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | power noise / noise simulation / Magnetic Probe / EMC / Power Integrity / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 315, ICD2010-83, pp. 1-6, Nov. 2010. | |
| Paper # | ICD2010-83 | |
| Date of Issue | 2010-11-22 (CPM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPM2010-124 ICD2010-83 Link to ES Tech. Rep. Archives: CPM2010-124 ICD2010-83 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2010-11-29 - 2010-12-01 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kyushu University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2010 ―New Field of VLSI Design― |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of frequency components of power noise in CMOS digital LSI |
| Sub Title (in English) | |
| Keyword(1) | power noise |
| Keyword(2) | noise simulation |
| Keyword(3) | Magnetic Probe |
| Keyword(4) | EMC |
| Keyword(5) | Power Integrity |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kumpei Yoshikawa |
| 1st Author's Affiliation | Kobe University (Kobe Univ.) |
| 2nd Author's Name | Hiroshi Matsumoto |
| 2nd Author's Affiliation | Kobe University (Kobe Univ.) |
| 3rd Author's Name | Yuta Sasaki |
| 3rd Author's Affiliation | Kobe University (Kobe Univ.) |
| 4th Author's Name | Makoto Nagata |
| 4th Author's Affiliation | Kobe University/CREST-JST (Kobe Univ./CREST-JST) |
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| Speaker | 1 |
| Date Time | 2010-11-29 10:40:00 |
| Presentation Time | 20 |
| Registration for | ICD |
| Paper # | IEICE-CPM2010-124,IEICE-ICD2010-83 |
| Volume (vol) | IEICE-110 |
| Number (no) | no.314(CPM), no.315(ICD) |
| Page | pp.1-6 |
| #Pages | IEICE-6 |
| Date of Issue | IEICE-CPM-2010-11-22,IEICE-ICD-2010-11-22 |
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