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| Presentation | 2010-11-12 10:55 Topography simulation of BiCS memory hole etching and modeling of SiO2 and Si etching Takashi Ichikawa, Daigo Ichinose, Kenji Kawabata, Naoki Tamaoki (Toshiba)  SDM2010-177 Link to ES Tech. Rep. Archives: SDM2010-177 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A topography simulation of BiCS memory hole etching is performed. The model parameters are fitted by elementary experiments of Si and SiO2 etching, and BiCS topography simulation is performed without parameter fitting. Our new model describes the experimental topography of BiCS memory hole, including taper angles and undercuts of stacked films. The point of the modeling is that it takes into consideration removal of adsorbed O atoms by reflected ions from tapered SiO2 sidewall. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Topography simulation / process simulation / etching / RIE / BiCS / memory / modeling / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 274, SDM2010-177, pp. 35-39, Nov. 2010. | |
| Paper # | SDM2010-177 | |
| Date of Issue | 2010-11-04 (SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2010-177 Link to ES Tech. Rep. Archives: SDM2010-177 |
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| Conference Information | |
| Committee | SDM |
| Conference Date | 2010-11-11 - 2010-11-12 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Process, Device, Circuit Simulations, etc |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2010-11-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Topography simulation of BiCS memory hole etching and modeling of SiO2 and Si etching |
| Sub Title (in English) | |
| Keyword(1) | Topography simulation |
| Keyword(2) | process simulation |
| Keyword(3) | etching |
| Keyword(4) | RIE |
| Keyword(5) | BiCS |
| Keyword(6) | memory |
| Keyword(7) | modeling |
| Keyword(8) | |
| 1st Author's Name | Takashi Ichikawa |
| 1st Author's Affiliation | Toshiba Corporation (Toshiba) |
| 2nd Author's Name | Daigo Ichinose |
| 2nd Author's Affiliation | Toshiba Corporation (Toshiba) |
| 3rd Author's Name | Kenji Kawabata |
| 3rd Author's Affiliation | Toshiba Corporation (Toshiba) |
| 4th Author's Name | Naoki Tamaoki |
| 4th Author's Affiliation | Toshiba Corporation (Toshiba) |
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| Speaker | Author-1 |
| Date Time | 2010-11-12 10:55:00 |
| Presentation Time | 25 minutes |
| Registration for | SDM |
| Paper # | SDM2010-177 |
| Volume (vol) | vol.110 |
| Number (no) | no.274 |
| Page | pp.35-39 |
| #Pages | 5 |
| Date of Issue | 2010-11-04 (SDM) |
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