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Paper Abstract and Keywords
Presentation 2010-10-23 14:55
State Machine design in Pulse Logic circuit by using Closed-loops
Yusaku Yamazaki, Keiichi Nagai, Masatoshi Sekine (TAT) NC2010-47
Abstract (in Japanese) (See Japanese page) 
(in English) We have proposed pulse logic circuit with logical variable defined by pulse signal.
Proposed a pulse logic device to simulate pulse neuron, and attempt to design a state machine logic pulse.
Moreover, as the smallest unit representing the state of the system, we propose to use multiple pulse logic devices connected to the closed-loops.
Input pulse signal sequences to the closed-loop, and assign output pulse signal sequences to the state.
In this paper, combining this closed-loops, trying to design a state machine, and discuss its application to the robot control circuit.
Keyword (in Japanese) (See Japanese page) 
(in English) Pulse Logic / Neural Net / Lie Argebra / State Machine / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 246, NC2010-47, pp. 29-34, Oct. 2010.
Paper # NC2010-47 
Date of Issue 2010-10-16 (NC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NC2010-47

Conference Information
Committee NC  
Conference Date 2010-10-23 - 2010-10-23 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu Inst. Tech. (Kitakyushu Sci. and Res. Park) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Implementation and Systemization of Neurocomputing 
Paper Information
Registration To NC 
Conference Code 2010-10-NC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) State Machine design in Pulse Logic circuit by using Closed-loops 
Sub Title (in English)  
Keyword(1) Pulse Logic  
Keyword(2) Neural Net  
Keyword(3) Lie Argebra  
Keyword(4) State Machine  
1st Author's Name Yusaku Yamazaki  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TAT)
2nd Author's Name Keiichi Nagai  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TAT)
3rd Author's Name Masatoshi Sekine  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TAT)
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Date Time 2010-10-23 14:55:00 
Presentation Time 25 
Registration for NC 
Paper # IEICE-NC2010-47 
Volume (vol) IEICE-110 
Number (no) no.246 
Page pp.29-34 
#Pages IEICE-6 
Date of Issue IEICE-NC-2010-10-16 

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