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Paper Abstract and Keywords
Presentation 2010-10-06 11:45
[Invited Talk] PI/SI/EMI simulation technology for high-speed electronic design
Hideki Asai (Shizuoka Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) A variety of noise problems, such as signal integrity, power integrity and electromagnetic interference have become very serious with progress of system integration technology. In this report, first, high-speed digital design issues are described. Next, the historical overview and the present status of the simulation technology for power/signal integrity and EMC design are described. Finally, the future trend, including 3-dimensional/full-wave techniques and many-core simulation scheme, is suggested for the overall solution in chip/package/board co-design.
Keyword (in Japanese) (See Japanese page) 
(in English) Signal Integrity / Power Integrity / Electromagnetic Interference / Chip-Package-Board Co-Design / 3D Simulation / Parallel Simulation / /  
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Conference Information
Committee CAS  
Conference Date 2010-10-06 - 2010-10-06 
Place (in Japanese) (See Japanese page) 
Place (in English) Makuhari Messe 
Topics (in Japanese) (See Japanese page) 
Topics (in English) CEATEC2010 
Paper Information
Registration To CAS 
Conference Code 2010-10-CAS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) PI/SI/EMI simulation technology for high-speed electronic design 
Sub Title (in English)  
Keyword(1) Signal Integrity  
Keyword(2) Power Integrity  
Keyword(3) Electromagnetic Interference  
Keyword(4) Chip-Package-Board Co-Design  
Keyword(5) 3D Simulation  
Keyword(6) Parallel Simulation  
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1st Author's Name Hideki Asai  
1st Author's Affiliation Shizuoka University (Shizuoka Univ.)
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Speaker Author-1 
Date Time 2010-10-06 11:45:00 
Presentation Time 60 minutes 
Registration for CAS 
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