Paper Abstract and Keywords |
Presentation |
2010-09-27 16:30
[Invited Talk]
An Automatic Test Generation Framework for Digitally-Assisted Analog Circuit Satoshi Komatsu, Mohamed Abbas (Univ. of Tokyo), Yasuo Furukawa (Advantest), Kunihiro Asada (Univ. of Tokyo) VLD2010-46 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents a new analog ATPG (AATPG) framework that generates near-optimal test stimulus for the digitally-assisted adaptive equalizers in high-speed serial links. Based on the dynamic-signature-based testing scheme developed recently, our AATPG utilizes a Genetic Algorithm (GA) which attempts to maximize the difference between the fault-free and faulty dynamic signatures of the target fault. Our test generation framework takes into account process variations and signal noise in selecting the test stimulus, which minimizes the number of misclassified devices. The experimental results on a 5-tap feed-forward adaptive equalizer demonstrate that the GA-tests generated by our framework can effectively detect faults that are hard to detect by the hand-crafted tests. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Digitally-Assisted Analog Circuit / Automatic Test Generation / Genetic Algorithm / Signature-Based Testing / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 210, VLD2010-46, pp. 25-30, Sept. 2010. |
Paper # |
VLD2010-46 |
Date of Issue |
2010-09-20 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2010-46 |
Conference Information |
Committee |
VLD |
Conference Date |
2010-09-27 - 2010-09-28 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kyoto Institute of Technology |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Physical design, etc |
Paper Information |
Registration To |
VLD |
Conference Code |
2010-09-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An Automatic Test Generation Framework for Digitally-Assisted Analog Circuit |
Sub Title (in English) |
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Keyword(1) |
Digitally-Assisted Analog Circuit |
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Automatic Test Generation |
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Genetic Algorithm |
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Signature-Based Testing |
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1st Author's Name |
Satoshi Komatsu |
1st Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
2nd Author's Name |
Mohamed Abbas |
2nd Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
3rd Author's Name |
Yasuo Furukawa |
3rd Author's Affiliation |
Advantest Corporation (Advantest) |
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Kunihiro Asada |
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The University of Tokyo (Univ. of Tokyo) |
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Speaker |
Author-1 |
Date Time |
2010-09-27 16:30:00 |
Presentation Time |
30 minutes |
Registration for |
VLD |
Paper # |
VLD2010-46 |
Volume (vol) |
vol.110 |
Number (no) |
no.210 |
Page |
pp.25-30 |
#Pages |
6 |
Date of Issue |
2010-09-20 (VLD) |
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