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Paper Abstract and Keywords
Presentation 2010-09-17 13:40
Implementation and Evaluation of ScalableCore System 2.0
Yoshito Sakaguchi, Shinya Takamaeda, Kenji Kise (Tokyo Tech) RECONF2010-38
Abstract (in Japanese) (See Japanese page) 
(in English) ScalableCore is a concept of prototyping system development by using a lot of FPGAs for Many-core architecture researches. In this paper, we present a new FPGA platform named ScalableCore system 2.0. This system realizes higher speed FPGA-FPGA communications than previous platform, ScalableCore System Version 1. We discussed the timing model of the system from basis of the observed communications speed. According to the timing model, we also estimate the simulation speed. To simulate a processor of 64 nodes, ScalableCore 2.0 is about 64 times faster than the software simulator; SimMc.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Many-core processor / evaluation environment / prototyping / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 204, RECONF2010-38, pp. 121-126, Sept. 2010.
Paper # RECONF2010-38 
Date of Issue 2010-09-09 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2010-38

Conference Information
Committee RECONF  
Conference Date 2010-09-16 - 2010-09-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Shizuoka University (Faculty of Eng., Hall 2) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2010-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation and Evaluation of ScalableCore System 2.0 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Many-core processor  
Keyword(3) evaluation environment  
Keyword(4) prototyping  
1st Author's Name Yoshito Sakaguchi  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Shinya Takamaeda  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name Kenji Kise  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Date Time 2010-09-17 13:40:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2010-38 
Volume (vol) IEICE-110 
Number (no) no.204 
Page pp.121-126 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2010-09-09 

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