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Paper Abstract and Keywords
Presentation 2010-09-17 09:25
COGRE: A Novel Compact Logic Cell Architecture for Area Reduction
Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-31
Abstract (in Japanese) (See Japanese page) 
(in English) In order to implement logic functions, conventional field programmable gate arrays (FPGAs) adopt look-up tables (LUTs) as programmable logic cells.
N-input LUTs can implement any N-input logic functions.
However, there is no need to use all logic functions in a circuit implementation.
Therefore, we can cut down the area and configuration memory bits of logic cells by decreasing the functionality.
In this paper, we propose a novel small-memory logic cell, COGRE, to minimize the FPGA area.
The experimental results show that the logic area in 6-COGRE is 46.3\% smaller than that in 6-LUT.
The logic area of 5-COGRE is 32.6\% smaller than that of 5-LUT and 10.0\% smaller than that of 4-LUT.
Further, the total number of configuration memory bits in 6-COGRE is 32.1\% smaller than the number of configuration memory bits in 6-LUT.
Keyword (in Japanese) (See Japanese page) 
(in English) reconfigurable logic device / logic cell / NPN equivalence class / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 204, RECONF2010-31, pp. 79-84, Sept. 2010.
Paper # RECONF2010-31 
Date of Issue 2010-09-09 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2010-31

Conference Information
Committee RECONF  
Conference Date 2010-09-16 - 2010-09-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Shizuoka University (Faculty of Eng., Hall 2) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2010-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) COGRE: A Novel Compact Logic Cell Architecture for Area Reduction 
Sub Title (in English)  
Keyword(1) reconfigurable logic device  
Keyword(2) logic cell  
Keyword(3) NPN equivalence class  
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1st Author's Name Yasuhiro Okamoto  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Yoshihiro Ichinomiya  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Motoki Amagasaki  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Toshinori Sueyoshi  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker
Date Time 2010-09-17 09:25:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2010-31 
Volume (vol) IEICE-110 
Number (no) no.204 
Page pp.79-84 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2010-09-09 


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