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Paper Abstract and Keywords
Presentation 2010-08-27 10:15
[Invited Talk] Development of sub-10um Thinning Technology using Actual Device Wafers
Nobuhide Maeda, Kim Youngsuk (Univ. of Tokyo), Yukinobu Hikosaka, Takashi Eshita (FSL), Hideki Kitada, Koji Fujimoto (Univ. of Tokyo), Yoriko Mizushima (Fujitsu Labs.), Kousuke Suzuki (DNP), Tomoji Nakamura (Fujitsu Labs.), Akihito Kawai, Kazuhisa Arai (DISCO), Takayuki Ohba (Univ. of Tokyo) SDM2010-141 ICD2010-56 Link to ES Tech. Rep. Archives: SDM2010-141 ICD2010-56
Abstract (in Japanese) (See Japanese page) 
(in English) 200-mm and 300-mm device wafers were successfully thinned down to less than 10-μm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50-nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9-μm, switching charge showed no change by the thinning process. CMOS logic device wafers thinned to 7-μm indicated neither change in Ion current nor junction leakage current. Thinning such wafers to <10-μm will allow for lower aspect ratio less than 4 of Through-Silicon-Via (TSV) in a via-last process.
Keyword (in Japanese) (See Japanese page) 
(in English) 3D Integration / Wafer thinning / WOW / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 182, SDM2010-141, pp. 95-97, Aug. 2010.
Paper # SDM2010-141 
Date of Issue 2010-08-19 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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Conference Information
Committee ICD SDM  
Conference Date 2010-08-26 - 2010-08-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Sapporo Center for Gender Equality 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Low voltage/low power techniques, novel devices, circuits, and applications 
Paper Information
Registration To SDM 
Conference Code 2010-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development of sub-10um Thinning Technology using Actual Device Wafers 
Sub Title (in English)  
Keyword(1) 3D Integration  
Keyword(2) Wafer thinning  
Keyword(3) WOW  
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1st Author's Name Nobuhide Maeda  
1st Author's Affiliation The University of Tokyo (Univ. of Tokyo)
2nd Author's Name Kim Youngsuk  
2nd Author's Affiliation The University of Tokyo (Univ. of Tokyo)
3rd Author's Name Yukinobu Hikosaka  
3rd Author's Affiliation Fujitsu Semiconductor Limited (FSL)
4th Author's Name Takashi Eshita  
4th Author's Affiliation Fujitsu Semiconductor Limited (FSL)
5th Author's Name Hideki Kitada  
5th Author's Affiliation The University of Tokyo (Univ. of Tokyo)
6th Author's Name Koji Fujimoto  
6th Author's Affiliation The University of Tokyo (Univ. of Tokyo)
7th Author's Name Yoriko Mizushima  
7th Author's Affiliation Fujitsu Laboratories Limited (Fujitsu Labs.)
8th Author's Name Kousuke Suzuki  
8th Author's Affiliation Dai Nippon Printing Co., Ltd. (DNP)
9th Author's Name Tomoji Nakamura  
9th Author's Affiliation Fujitsu Laboratories Limited (Fujitsu Labs.)
10th Author's Name Akihito Kawai  
10th Author's Affiliation DISCO Corporation (DISCO)
11th Author's Name Kazuhisa Arai  
11th Author's Affiliation DISCO Corporation (DISCO)
12th Author's Name Takayuki Ohba  
12th Author's Affiliation The University of Tokyo (Univ. of Tokyo)
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Speaker
Date Time 2010-08-27 10:15:00 
Presentation Time 50 
Registration for SDM 
Paper # IEICE-SDM2010-141,IEICE-ICD2010-56 
Volume (vol) IEICE-110 
Number (no) no.182(SDM), no.183(ICD) 
Page pp.95-97 
#Pages IEICE-3 
Date of Issue IEICE-SDM-2010-08-19,IEICE-ICD-2010-08-19 


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