IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-08-27 16:25
On the Gate-Stack Origin Threshold Voltage Variability in Scaled FinFETs and Multi-FinFETs
Yongxun Liu, Kazuhiko Endo, Shinich Ouchi (AIST), Takahiro Kamei (Meiji Univ.), Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa (AIST), Tetsuro Hayashida (Meiji Univ.), Kunihiro Sakamoto, Takashi Matsukawa (AIST), Atsushi Ogura (Meiji Univ.), Meishoku Masahara (AIST) SDM2010-151 ICD2010-66 Link to ES Tech. Rep. Archives: SDM2010-151 ICD2010-66
Abstract (in Japanese) (See Japanese page) 
(in English) The threshold voltage (Vt) variability in scaled FinFETs with gate length down to 20 nm was systematically investigated. It was found that the atomically flat Si-fin sidewall channels fabricated by using the orientation dependent wet etching are very effective to reduce the gate-stack origin Vt variations (VTV). By investigating the gate oxide thickness (Tox) dependence of VTV, the gate-stack origin, i.e., work function variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. Moreover, it was experimentally found that the Vt of the scaled P-channel PVD-TiN gate multi-FinFETs with the same gate area reduces with increasing the number of fins.
Keyword FinFET,Threshold Voltage, Variability
Keyword (in Japanese) (See Japanese page) 
(in English) FinFET / Threshold Voltage / Variability / Gate work function / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 182, SDM2010-151, pp. 149-154, Aug. 2010.
Paper # SDM2010-151 
Date of Issue 2010-08-19 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2010-151 ICD2010-66 Link to ES Tech. Rep. Archives: SDM2010-151 ICD2010-66

Conference Information
Committee ICD SDM  
Conference Date 2010-08-26 - 2010-08-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Sapporo Center for Gender Equality 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Low voltage/low power techniques, novel devices, circuits, and applications 
Paper Information
Registration To SDM 
Conference Code 2010-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On the Gate-Stack Origin Threshold Voltage Variability in Scaled FinFETs and Multi-FinFETs 
Sub Title (in English)  
Keyword(1) FinFET  
Keyword(2) Threshold Voltage  
Keyword(3) Variability  
Keyword(4) Gate work function  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yongxun Liu  
1st Author's Affiliation National Institute of AIST (AIST)
2nd Author's Name Kazuhiko Endo  
2nd Author's Affiliation National Institute of AIST (AIST)
3rd Author's Name Shinich Ouchi  
3rd Author's Affiliation National Institute of AIST (AIST)
4th Author's Name Takahiro Kamei  
4th Author's Affiliation Meiji University (Meiji Univ.)
5th Author's Name Junichi Tsukada  
5th Author's Affiliation National Institute of AIST (AIST)
6th Author's Name Hiromi Yamauchi  
6th Author's Affiliation National Institute of AIST (AIST)
7th Author's Name Yuki Ishikawa  
7th Author's Affiliation National Institute of AIST (AIST)
8th Author's Name Tetsuro Hayashida  
8th Author's Affiliation Meiji University (Meiji Univ.)
9th Author's Name Kunihiro Sakamoto  
9th Author's Affiliation National Institute of AIST (AIST)
10th Author's Name Takashi Matsukawa  
10th Author's Affiliation National Institute of AIST (AIST)
11th Author's Name Atsushi Ogura  
11th Author's Affiliation Meiji University (Meiji Univ.)
12th Author's Name Meishoku Masahara  
12th Author's Affiliation National Institute of AIST (AIST)
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker
Date Time 2010-08-27 16:25:00 
Presentation Time 25 
Registration for SDM 
Paper # IEICE-SDM2010-151,IEICE-ICD2010-66 
Volume (vol) IEICE-110 
Number (no) no.182(SDM), no.183(ICD) 
Page pp.149-154 
#Pages IEICE-6 
Date of Issue IEICE-SDM-2010-08-19,IEICE-ICD-2010-08-19 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan