Paper Abstract and Keywords |
Presentation |
2010-08-26 09:10
On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores utilizing Parasitic Capacitance of Sleep Blocks Jinmyoung Kim, Toru Nakura (Univ. of Tokyo.), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.) SDM2010-124 ICD2010-39 Link to ES Tech. Rep. Archives: SDM2010-124 ICD2010-39 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper proposes an on-chip supply resonance noise reduction method for multi-IP cores utilizing parasitic capacitance of sleep blocks. It has smaller area penalty than conventional on-chip large MOS capacitors because we use parasitic capacitance of sleep blocks for noise cancelling. Measurement results show that the test chip fabricated in a 0.18um CMOS process achieved 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. These results make fast power mode transition possible for dynamic voltage scaling and power gating. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Power supply noise / resonance / parasitic capacitance / sleep block / DVS / power gating / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 183, ICD2010-39, pp. 1-4, Aug. 2010. |
Paper # |
ICD2010-39 |
Date of Issue |
2010-08-19 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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SDM2010-124 ICD2010-39 Link to ES Tech. Rep. Archives: SDM2010-124 ICD2010-39 |
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