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Paper Abstract and Keywords
Presentation 2010-08-26 14:15
Power Analysis and Power Reduction Techniques of a 128GFLOPS/58W SPARC64VIIIfx Processor for Peta-scale Computing
Yukihito Kawabe (Fujitsu Lab.), Hiroshi Okano, Ryuji Kan, Toshio Yoshida, Iwao Yamazaki, Hitoshi Sakurai, Mikio Hondou, Nobuyuki Matsui, Hideo Yamashita, Tatsumi Nakada, Takumi Maruyama, Takeo Asakawa (Fujitsu) SDM2010-134 ICD2010-49 Link to ES Tech. Rep. Archives: SDM2010-134 ICD2010-49
Abstract (in Japanese) (See Japanese page) 
(in English) We developed an 8-core SPARC64™ VIIIfx processor for Fujitsu’s next generation Super Computer. Micro-architecture and circuit level power reduction techniques are developed and measurement results show the processor achieves power consumption of 58W under executing a program for peak power consumption. In this papwer, we explain some of the power reduction techniques and power analysis flow.
Keyword (in Japanese) (See Japanese page) 
(in English) processor / HPC / power analysis / low power / ASV / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 183, ICD2010-49, pp. 55-58, Aug. 2010.
Paper # ICD2010-49 
Date of Issue 2010-08-19 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2010-134 ICD2010-49 Link to ES Tech. Rep. Archives: SDM2010-134 ICD2010-49

Conference Information
Committee ICD SDM  
Conference Date 2010-08-26 - 2010-08-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Sapporo Center for Gender Equality 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Low voltage/low power techniques, novel devices, circuits, and applications 
Paper Information
Registration To ICD 
Conference Code 2010-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Power Analysis and Power Reduction Techniques of a 128GFLOPS/58W SPARC64VIIIfx Processor for Peta-scale Computing 
Sub Title (in English)  
Keyword(1) processor  
Keyword(2) HPC  
Keyword(3) power analysis  
Keyword(4) low power  
Keyword(5) ASV  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yukihito Kawabe  
1st Author's Affiliation Fujitsu Laboratories Limited (Fujitsu Lab.)
2nd Author's Name Hiroshi Okano  
2nd Author's Affiliation Fujitsu Limited (Fujitsu)
3rd Author's Name Ryuji Kan  
3rd Author's Affiliation Fujitsu Limited (Fujitsu)
4th Author's Name Toshio Yoshida  
4th Author's Affiliation Fujitsu Limited (Fujitsu)
5th Author's Name Iwao Yamazaki  
5th Author's Affiliation Fujitsu Limited (Fujitsu)
6th Author's Name Hitoshi Sakurai  
6th Author's Affiliation Fujitsu Limited (Fujitsu)
7th Author's Name Mikio Hondou  
7th Author's Affiliation Fujitsu Limited (Fujitsu)
8th Author's Name Nobuyuki Matsui  
8th Author's Affiliation Fujitsu Limited (Fujitsu)
9th Author's Name Hideo Yamashita  
9th Author's Affiliation Fujitsu Limited (Fujitsu)
10th Author's Name Tatsumi Nakada  
10th Author's Affiliation Fujitsu Limited (Fujitsu)
11th Author's Name Takumi Maruyama  
11th Author's Affiliation Fujitsu Limited (Fujitsu)
12th Author's Name Takeo Asakawa  
12th Author's Affiliation Fujitsu Limited (Fujitsu)
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Speaker
Date Time 2010-08-26 14:15:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-SDM2010-134,IEICE-ICD2010-49 
Volume (vol) IEICE-110 
Number (no) no.182(SDM), no.183(ICD) 
Page pp.55-58 
#Pages IEICE-4 
Date of Issue IEICE-SDM-2010-08-19,IEICE-ICD-2010-08-19 


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