Paper Abstract and Keywords |
Presentation |
2010-08-05 14:00
Implementaton and evaluation of light weight high speed serial communications with Error Correcting Code Yoshito Sakaguchi, Mochamad Asri, Shinya Takamaeda, Haruhiko Kaneko, Kenji Kise (Tokyo Inst. of Tech.) CPSY2010-19 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Errror correcting code is required, which is capable enough of correctiong errors, implementable with
low resources and highspeed. Sawa proposed a code to achieve these requirements. We focus on this code. We
implement the encoder and the decoder on FPGAs and evaluate the code. The result shows that the decoder can
be implimented with 260 of 4 input LUTs , the code is decodable in 3 cycles and acheives lower error rate than
SEC-DED(sigle error correction - double error detection) code. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / ECC / serial communications / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 167, CPSY2010-19, pp. 67-72, Aug. 2010. |
Paper # |
CPSY2010-19 |
Date of Issue |
2010-07-28 (CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2010-19 |
Conference Information |
Committee |
CPSY DC |
Conference Date |
2010-08-03 - 2010-08-05 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kanazawa Cultural Hall |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Summer United Workshops on Parallel, Distributed and Cooperative Processing |
Paper Information |
Registration To |
CPSY |
Conference Code |
2010-08-CPSY-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Implementaton and evaluation of light weight high speed serial communications with Error Correcting Code |
Sub Title (in English) |
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Keyword(1) |
FPGA |
Keyword(2) |
ECC |
Keyword(3) |
serial communications |
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1st Author's Name |
Yoshito Sakaguchi |
1st Author's Affiliation |
Tokyo Institute of Technology (Tokyo Inst. of Tech.) |
2nd Author's Name |
Mochamad Asri |
2nd Author's Affiliation |
Tokyo Institute of Technology (Tokyo Inst. of Tech.) |
3rd Author's Name |
Shinya Takamaeda |
3rd Author's Affiliation |
Tokyo Institute of Technology (Tokyo Inst. of Tech.) |
4th Author's Name |
Haruhiko Kaneko |
4th Author's Affiliation |
Tokyo Institute of Technology (Tokyo Inst. of Tech.) |
5th Author's Name |
Kenji Kise |
5th Author's Affiliation |
Tokyo Institute of Technology (Tokyo Inst. of Tech.) |
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Speaker |
Author-1 |
Date Time |
2010-08-05 14:00:00 |
Presentation Time |
30 minutes |
Registration for |
CPSY |
Paper # |
CPSY2010-19 |
Volume (vol) |
vol.110 |
Number (no) |
no.167 |
Page |
pp.67-72 |
#Pages |
6 |
Date of Issue |
2010-07-28 (CPSY) |
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