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Paper Abstract and Keywords
Presentation 2010-07-23 09:40
OTA Design Using gm/ID Lookup Table Methodology -- Design optimization featuring settling time analysis --
Toru Kashimura, Takayuki Konishi, Shoichi Masui (Tohoku Univ.) ICD2010-31 Link to ES Tech. Rep. Archives: ICD2010-31
Abstract (in Japanese) (See Japanese page) 
(in English) Settling time is a primary design parameter in operational transconductance amplifiers (OTAs) used for high-speed applications such as pipeline A/D converters. For scaled CMOS technologies, an OTA design methodology using gm/ID lookup tables has been proposed to minimize its power consumption. A major problem in the conventionally proposed method is that settling time was not included in a target specification, but was converted into crossover frequency fc with an empirical approach. In this paper, we introduce an iterative optimization sequence to design OTAs, which can achieve the target settling time with the minimum power consumptions.
Keyword (in Japanese) (See Japanese page) 
(in English) operational transconductance amplifier / design optimization / settling time optimization / low power design / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 140, ICD2010-31, pp. 61-66, July 2010.
Paper # ICD2010-31 
Date of Issue 2010-07-15 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2010-31 Link to ES Tech. Rep. Archives: ICD2010-31

Conference Information
Committee ICD ITE-IST  
Conference Date 2010-07-22 - 2010-07-23 
Place (in Japanese) (See Japanese page) 
Place (in English) Josho Gakuen Osaka Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed analog and digital, RF, and sensor interface circuitry 
Paper Information
Registration To ICD 
Conference Code 2010-07-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) OTA Design Using gm/ID Lookup Table Methodology 
Sub Title (in English) Design optimization featuring settling time analysis 
Keyword(1) operational transconductance amplifier  
Keyword(2) design optimization  
Keyword(3) settling time optimization  
Keyword(4) low power design  
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1st Author's Name Toru Kashimura  
1st Author's Affiliation Tohoku Univercity (Tohoku Univ.)
2nd Author's Name Takayuki Konishi  
2nd Author's Affiliation Tohoku Univercity (Tohoku Univ.)
3rd Author's Name Shoichi Masui  
3rd Author's Affiliation Tohoku Univercity (Tohoku Univ.)
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Speaker Author-1 
Date Time 2010-07-23 09:40:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2010-31 
Volume (vol) vol.110 
Number (no) no.140 
Page pp.61-66 
#Pages
Date of Issue 2010-07-15 (ICD) 


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