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| Presentation | 2010-06-25 13:30 A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST)  DC2010-8 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Using asynchronous VLSI designs resolve synchronous circuit design difficulties, e.g.\ the clock skew, higher throughput and lower power consumption. ITRS predicts that a globally-asynchronous, locally-synchronous (GALS) design scheme will be adopted for various applications in near future. Although a full scan design method for synchronous circuits is applied to asynchronous circuits to achieve the same testability of their combinational parts, the overhead is extremely high. To reduce the overhead, several full scan design methods have been proposed but they cannot guarantee complete test. In this paper, we propose a bipartite full scan design as a new DFT method for asynchronous circuits where we guarantee complete test for both combinational and sequential parts of circuits with area and performance overhead comparable to the previous best method in terms of overhead. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Asynchronous circuit testing / L1L2* full scan design / bipartite full scan testability / scannable C-element / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 106, DC2010-8, pp. 1-6, June 2010. | |
| Paper # | DC2010-8 | |
| Date of Issue | 2010-06-18 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2010-8 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2010-06-25 - 2010-06-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2010-06-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous circuit testing |
| Keyword(2) | L1L2* full scan design |
| Keyword(3) | bipartite full scan testability |
| Keyword(4) | scannable C-element |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hiroshi Iwata |
| 1st Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 2nd Author's Name | Satoshi Ohtake |
| 2nd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 3rd Author's Name | Michiko Inoue |
| 3rd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 4th Author's Name | Hideo Fujiwara |
| 4th Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
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| Speaker | Author-1 |
| Date Time | 2010-06-25 13:30:00 |
| Presentation Time | 30 minutes |
| Registration for | DC |
| Paper # | DC2010-8 |
| Volume (vol) | vol.110 |
| Number (no) | no.106 |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2010-06-18 (DC) |
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