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| Presentation | 2010-06-18 15:40 Examination of output circuit for far-end crosstalk decrease Suguru Kato, Shinichi Sasaki (Saga Univ.)  EMCJ2010-19 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With development of information instruments, the crosstalk decrease between signal wires in wiring board and wiring in LSI becomes an important problem. The crosstalk is possible to decrease by being a gradual rise and fall time of two propagation mode or reducing slewrate of signal. In this paper, in order to realize the automation of variable slewrate according to a system clock, defined relation between clock frequency and optimum slewrate, and it proposed the control circuit to automatically control. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Crosstalk / Slewrate / FG-MOS Transistor / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 84, EMCJ2010-19, pp. 67-72, June 2010. | |
| Paper # | EMCJ2010-19 | |
| Date of Issue | 2010-06-11 (EMCJ) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | EMCJ2010-19 |
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| Conference Information | |
| Committee | EMCJ IEE-EMC |
| Conference Date | 2010-06-18 - 2010-06-18 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Osaka Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Electric Power, EMC, etc. |
| Paper Information | |
| Registration To | EMCJ |
| Conference Code | 2010-06-EMCJ-EMC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Examination of output circuit for far-end crosstalk decrease |
| Sub Title (in English) | |
| Keyword(1) | Crosstalk |
| Keyword(2) | Slewrate |
| Keyword(3) | FG-MOS Transistor |
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| 1st Author's Name | Suguru Kato |
| 1st Author's Affiliation | Saga University (Saga Univ.) |
| 2nd Author's Name | Shinichi Sasaki |
| 2nd Author's Affiliation | Saga University (Saga Univ.) |
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| Speaker | Author-1 |
| Date Time | 2010-06-18 15:40:00 |
| Presentation Time | 25 minutes |
| Registration for | EMCJ |
| Paper # | EMCJ2010-19 |
| Volume (vol) | vol.110 |
| Number (no) | no.84 |
| Page | pp.67-72 |
| #Pages | 6 |
| Date of Issue | 2010-06-11 (EMCJ) |
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