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Paper Abstract and Keywords
Presentation 2010-05-21 10:25
Implementation and Evaluation of a Low-Power TCP/IP Offload Engine for 1 Gbps Ethernet
Shingo Tanaka, Takahiro Yamaura, Nobuhiko Sugasawa, Yoshimichi Tanizawa, Kensaku Yamaguchi, Naohisa Shibuya (Toshiba Corporation) NS2010-25
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, an increasingly large amount of high-definition video is being streamed over various networks such as the Internet. TCP/IP is commonly used as a standard communication protocol on those networks, and most of the time the protocol is processed by CPUs. However, the higher CPU processing power needed in order to handle the large amount of data being carried by video streams, etc., has been causing several issues such as higher required operating frequency and/or increased power consumption, especially in embedded systems. In order to solve these issues, we have designed and implemented a hardware-based TCP/IP offload engine, called NPEngineTM. Compared to a conventional embedded CPU, NPEngineTM achieves about 80 times higher throughput at the same operating frequency, and 22 to 28 times higher throughput at the same power consumption. In this paper, we describe NPEngineTM focusing on its key design aspects (hybrid processing, direct data transfer and pipelined processing), and its performance evaluation results.
Keyword (in Japanese) (See Japanese page) 
(in English) TCP/IP / Offload Engine / Dedicated Circuit / Accelerator / FPGA / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 39, NS2010-25, pp. 53-58, May 2010.
Paper # NS2010-25 
Date of Issue 2010-05-13 (NS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NS2010-25

Conference Information
Committee NS  
Conference Date 2010-05-20 - 2010-05-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Advanced Protocol and Network Control (Application level routing, QoS and Path Control, P2P, P4P, SIP), Network System Architecture (Interface, Hardware, Software) 
Paper Information
Registration To NS 
Conference Code 2010-05-NS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation and Evaluation of a Low-Power TCP/IP Offload Engine for 1 Gbps Ethernet 
Sub Title (in English)  
Keyword(1) TCP/IP  
Keyword(2) Offload Engine  
Keyword(3) Dedicated Circuit  
Keyword(4) Accelerator  
Keyword(5) FPGA  
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Keyword(7)  
Keyword(8)  
1st Author's Name Shingo Tanaka  
1st Author's Affiliation Toshiba Corporation (Toshiba Corporation)
2nd Author's Name Takahiro Yamaura  
2nd Author's Affiliation Toshiba Corporation (Toshiba Corporation)
3rd Author's Name Nobuhiko Sugasawa  
3rd Author's Affiliation Toshiba Corporation (Toshiba Corporation)
4th Author's Name Yoshimichi Tanizawa  
4th Author's Affiliation Toshiba Corporation (Toshiba Corporation)
5th Author's Name Kensaku Yamaguchi  
5th Author's Affiliation Toshiba Corporation (Toshiba Corporation)
6th Author's Name Naohisa Shibuya  
6th Author's Affiliation Toshiba Corporation (Toshiba Corporation)
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Speaker Author-1 
Date Time 2010-05-21 10:25:00 
Presentation Time 25 minutes 
Registration for NS 
Paper # NS2010-25 
Volume (vol) vol.110 
Number (no) no.39 
Page pp.53-58 
#Pages
Date of Issue 2010-05-13 (NS) 


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