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| Presentation | 2010-05-20 13:05 A Wide-Range Clock Synchronizer with Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS Control Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu (Hitachi), Yoshihiko Yasu, Koichiro Ishibashi (Renesas)  VLD2010-7 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A ``wide-range voltage-and-frequency clock synchronizer'' for maintaining synchronization during voltage-scaling transition in dynamic voltage-and-frequency scaling (DVFS) was developed. The key feature of the synchronizer is so-called predictive-delay-adjustment scheme based on a relative skew measure. The scheme reduces the area of the WRCS by 77\%. The area of the fabricated WRCS in a 40-nm CMOS is only 5.65$\times$10$^{-3}$ mm$^2$. It was demonstrated for the first time that measured skew is suppressed to less than 6.8\% of clock period in the case of wide-range voltage variation (0.8 -- 1.55 V) and wide frequency range (100 MHz -- 1 GHz). Moreover, current dissipation of the synchronizer is only 0.48 mA at 1.1-V 100-MHz operation. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Clock synchronizer / DVFS control / low power / multicore SoC / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 36, VLD2010-7, pp. 67-72, May 2010. | |
| Paper # | VLD2010-7 | |
| Date of Issue | 2010-05-12 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2010-7 |
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| Conference Information | |
| Committee | VLD IPSJ-SLDM |
| Conference Date | 2010-05-19 - 2010-05-20 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System Design, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2010-05-VLD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Wide-Range Clock Synchronizer with Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS Control |
| Sub Title (in English) | |
| Keyword(1) | Clock synchronizer |
| Keyword(2) | DVFS control |
| Keyword(3) | low power |
| Keyword(4) | multicore SoC |
| Keyword(5) | |
| Keyword(6) | |
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| Keyword(8) | |
| 1st Author's Name | Masafumi Onouchi |
| 1st Author's Affiliation | Hitachi Ltd. Central Research Lab. (Hitachi) |
| 2nd Author's Name | Yusuke Kanno |
| 2nd Author's Affiliation | Hitachi Ltd. Central Research Lab. (Hitachi) |
| 3rd Author's Name | Makoto Saen |
| 3rd Author's Affiliation | Hitachi Ltd. Central Research Lab. (Hitachi) |
| 4th Author's Name | Shigenobu Komatsu |
| 4th Author's Affiliation | Hitachi Ltd. Central Research Lab. (Hitachi) |
| 5th Author's Name | Yoshihiko Yasu |
| 5th Author's Affiliation | Renesas Electronics Corporation (Renesas) |
| 6th Author's Name | Koichiro Ishibashi |
| 6th Author's Affiliation | Renesas Electronics Corporation (Renesas) |
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| Speaker | Author-1 |
| Date Time | 2010-05-20 13:05:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2010-7 |
| Volume (vol) | vol.110 |
| Number (no) | no.36 |
| Page | pp.67-72 |
| #Pages | 6 |
| Date of Issue | 2010-05-12 (VLD) |
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