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Paper Abstract and Keywords
Presentation 2010-05-14 13:40
Implementation of Arithmetic Pipeline on FLOPS-2D:Multi-FPGA Platform
Hirokazu Morishita, Kenta Inakagata (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) RECONF2010-16
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, CFD has been attracted as a useful simulation method for aerocraft components. UPACS, one of the practical CFD packages, supports various selectability and has high versatility. In this work, a custom machine for efficient execution of MUSCL; a core function in UPACS was implemented on FLOPS-2D: Multi-FPGA reconfigurable system. To implement on FLOPS-2D, the deep and complicated arithmetic pipeline generated from MUSCL dataflow was divided into two FPGA boards, then each divided pipeline was optimized by a tuning tool called RER. With optimization of the order of operations and pipeline structure, about 60 % utilization of the pipeline is achieved even by using serial links between two boards. The execution time is 6.16-23.19 times faster than that of the software on 2.66 GHz Intel Core 2 Duo processor.
Keyword (in Japanese) (See Japanese page) 
(in English) Multi-FPGA system / CFD / Acceleration / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 32, RECONF2010-16, pp. 87-92, May 2010.
Paper # RECONF2010-16 
Date of Issue 2010-05-06 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee RECONF  
Conference Date 2010-05-13 - 2010-05-14 
Place (in Japanese) (See Japanese page) 
Place (in English)  
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Paper Information
Registration To RECONF 
Conference Code 2010-05-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation of Arithmetic Pipeline on FLOPS-2D:Multi-FPGA Platform 
Sub Title (in English)  
Keyword(1) Multi-FPGA system  
Keyword(2) CFD  
Keyword(3) Acceleration  
1st Author's Name Hirokazu Morishita  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Kenta Inakagata  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Yasunori Osana  
3rd Author's Affiliation Seikei University (Seikei Univ.)
4th Author's Name Naoyuki Fujita  
4th Author's Affiliation Japan Aerospace Exploration Agency (JAXA)
5th Author's Name Hideharu Amano  
5th Author's Affiliation Keio University (Keio Univ.)
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Date Time 2010-05-14 13:40:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2010-16 
Volume (vol) IEICE-110 
Number (no) no.32 
Page pp.87-92 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2010-05-06 

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