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Paper Abstract and Keywords
Presentation 2010-05-14 13:15
An Efficient Implementation of Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs
Yasuaki Ito, Koji Nakano (Hiroshima Univ.) RECONF2010-15
Abstract (in Japanese) (See Japanese page) 
(in English) Consider the following operation on an arbitrary positive number: if the number is even, divide it by two, and if the number is odd, triple it and add one. The Collatz conjecture asserts that, starting from any positive number $m$, repeated iteration of the operations eventually produces the value $1$. The main contribution of this paper is to present an efficient implementation of a coprocessor that performs the exhaustive search to verify the Collatz conjecture using a DSP48E Xilinx Virtex-5 blocks, each of which contains one multiplier and one adder. The experimental results show that, our coprocessor can verify $3.88\times 10^8$ 64-bit numbers per second.
Keyword (in Japanese) (See Japanese page) 
(in English) Hardware Algorithm / Collatz conjecture / FPGA Implementation / DSP blocks / Block RAMs / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 32, RECONF2010-15, pp. 81-86, May 2010.
Paper # RECONF2010-15 
Date of Issue 2010-05-06 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee RECONF  
Conference Date 2010-05-13 - 2010-05-14 
Place (in Japanese) (See Japanese page) 
Place (in English)  
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Paper Information
Registration To RECONF 
Conference Code 2010-05-RECONF 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Efficient Implementation of Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs 
Sub Title (in English)  
Keyword(1) Hardware Algorithm  
Keyword(2) Collatz conjecture  
Keyword(3) FPGA Implementation  
Keyword(4) DSP blocks  
Keyword(5) Block RAMs  
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1st Author's Name Yasuaki Ito  
1st Author's Affiliation Hiroshima University (Hiroshima Univ.)
2nd Author's Name Koji Nakano  
2nd Author's Affiliation Hiroshima University (Hiroshima Univ.)
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Speaker
Date Time 2010-05-14 13:15:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2010-15 
Volume (vol) IEICE-110 
Number (no) no.32 
Page pp.81-86 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2010-05-06 


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