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| Presentation | 2010-05-13 14:55 A study on multicore designed MuCCRA3 : dynamically reconfigurable processor array Eiichi Sasaki, Yoshiki Saito, Masayuki Kimura, Hideharu Amano (Keio Univ.)  RECONF2010-4 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recently, since a mobile device is required to provide various functions, a lot of specialized hardware modules must be embedded to fulfill required functions and performance. However, increasing number of embedded specialized hardware causes problems about developmental cost, area and power consumption. For solving these problems, Dynamically Reconfigurable Processor Array (DRPA) attracts attention as a flexible accelerator instead of specialized hardware. For using DRPAs instead of multiple specialized hardware, a single PE array often cannot support enough performance. That is, multi-core DRPA has become popular. In this study, we extended a DRPA MuCCRA-3 to a multi-core system, and evaluated its area and performance. By attaching a multi-task allocation mechanism, transfer buffer for cores, and shared memory to multiple MuCCRA-3 arrays, MuCCRA-3 Multicore (MuCCRA-3M) is formed. As a result of performance evaluation, 3-core MuCCRA-3M achieves about 2.7 times better performance than a single-core MuCCRA-3, by using pipelined task execution. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Dynamically Reconfigurable System / Multi-core System / Embendded System / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 32, RECONF2010-4, pp. 19-24, May 2010. | |
| Paper # | RECONF2010-4 | |
| Date of Issue | 2010-05-06 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2010-4 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2010-05-13 - 2010-05-14 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2010-05-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A study on multicore designed MuCCRA3 : dynamically reconfigurable processor array |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable System |
| Keyword(2) | Multi-core System |
| Keyword(3) | Embendded System |
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| 1st Author's Name | Eiichi Sasaki |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Yoshiki Saito |
| 2nd Author's Affiliation | Keio University (Keio Univ.) |
| 3rd Author's Name | Masayuki Kimura |
| 3rd Author's Affiliation | Keio University (Keio Univ.) |
| 4th Author's Name | Hideharu Amano |
| 4th Author's Affiliation | Keio University (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2010-05-13 14:55:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2010-4 |
| Volume (vol) | vol.110 |
| Number (no) | no.32 |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2010-05-06 (RECONF) |
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