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| Presentation | 2010-05-13 15:20 First Prototype Chip of a Non-Volatile Reconfigurable Logic using FeRAM Cells Masahiro Koga, Masahiro Iida, Motoki Amagasaki (Kumamoto Univ.), Yoshinobu Ichida, Mitsuro Saji, Jun Iida (ROHM), Toshinori Sueyoshi (Kumamoto Univ.)  RECONF2010-5 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | An advantage of a RLD such as an FPGA is that it can be customized after being manufactured. However, there is a problem related to standby power when using it in SoC used in embedded systems. Power gating, which is one of the power reduction techniques, is difficult to use in SRAM-based RLDs because of the high overhea and SRAM being volatile. In this paper, we describe a chip that we developed --- a reconfigurable logic chip based on FeRAM technology. The chip uses a variable grain logic cell as a logic block. A NV-FF (Non-Volatile FlipFlop), which contains FeRAM, a FF, and power-gating control circuits, is used as configuration memory. The NV-FF can transmit data between FeRAM and FF automatically when power to the chip is turned off/on. The hibernate/restore time is less than 1 ms. The chip has 18 $\times$ 18 logic blocks and an area of 54.76 mm$^2$. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Prototype / Reconfigurable logic / Power gating / Non-volatile memory / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 32, RECONF2010-5, pp. 25-30, May 2010. | |
| Paper # | RECONF2010-5 | |
| Date of Issue | 2010-05-06 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2010-5 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2010-05-13 - 2010-05-14 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2010-05-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | First Prototype Chip of a Non-Volatile Reconfigurable Logic using FeRAM Cells |
| Sub Title (in English) | |
| Keyword(1) | Prototype |
| Keyword(2) | Reconfigurable logic |
| Keyword(3) | Power gating |
| Keyword(4) | Non-volatile memory |
| Keyword(5) | |
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| Keyword(8) | |
| 1st Author's Name | Masahiro Koga |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 2nd Author's Name | Masahiro Iida |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 3rd Author's Name | Motoki Amagasaki |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 4th Author's Name | Yoshinobu Ichida |
| 4th Author's Affiliation | ROHM Co., Ltd. (ROHM) |
| 5th Author's Name | Mitsuro Saji |
| 5th Author's Affiliation | ROHM Co., Ltd. (ROHM) |
| 6th Author's Name | Jun Iida |
| 6th Author's Affiliation | ROHM Co., Ltd. (ROHM) |
| 7th Author's Name | Toshinori Sueyoshi |
| 7th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2010-05-13 15:20:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2010-5 |
| Volume (vol) | vol.110 |
| Number (no) | no.32 |
| Page | pp.25-30 |
| #Pages | 6 |
| Date of Issue | 2010-05-06 (RECONF) |
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